| /llvm-project-15.0.7/llvm/test/MC/AMDGPU/ |
| H A D | gfx11_asm_dpp.s | 19 ; VOP2->3
124 ; VOP2->3
144 ; VOP2
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | AMDGPUInstructionSyntax.rst | 144 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
153 *VOP1*, *VOP2* and *VOPC* (32-bit) encoding _e32
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| H A D | AMDGPUUsage.rst | 14486 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
14490 * _e32 for 32-bit VOP1/VOP2/VOPC
14495 VOP1/VOP2/VOP3/VOPC examples:
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | verify-constant-bus-violations.mir | 22 # GFX10PLUS-ERR: *** Bad machine code: VOP2/VOP3 instruction uses more than one literal ***
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| H A D | sdwa-vop2-64bit.mir | 5 # No conversion for VOP2 instructions that have only 64-bit encoding
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| H A D | dpp_combine.mir | 8 # VOP2:
27 ; VOP2
58 # VOP2:
111 ; VOP2
564 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
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| H A D | dpp_combine_gfx11.mir | 452 # Test instruction which does not have modifiers in VOP2 form but does in DPP form.
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrFormats.td | 29 field bit VOP2 = 0;
164 let TSFlags{8} = VOP2;
237 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| H A D | VOP2Instructions.td | 10 // VOP2 Classes
76 let VOP2 = 1;
89 let VOP2 = 1;
589 // VOP2 Instructions
1105 //===------------------------------- VOP2 -------------------------------===//
1138 //===------------------------- VOP2 (with name) -------------------------===//
1348 //===------------------------------- VOP2 -------------------------------===//
1394 //===------------------------- VOP2 (with name) -------------------------===//
1622 // VOP2 no carry-in, carry-out.
1630 // VOP2 carry-in, carry-out.
[all …]
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| H A D | SIDefines.h | 41 VOP2 = 1 << 8, enumerator
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| H A D | SIInstrInfo.h | 432 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
436 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| H A D | VOP3Instructions.td | 953 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11<0x360>; // Pseudo in VOP2
955 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11<0x361>; // Pseudo in VOP2
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| H A D | VOPInstructions.td | 1438 // VOP1 and VOP2 depend on these triple defs
1492 def VOP2InfoTable : VOPInfoTable<"VOP2">;
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| H A D | SIInstrInfo.td | 1587 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1784 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1824 // VOP2 without modifiers
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| H A D | SIInstructions.td | 962 // VOP2 Patterns
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| /llvm-project-15.0.7/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX1011.rst | 56 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX906.rst | 36 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX908.rst | 56 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX7.rst | 719 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX8.rst | 866 VOP2 section in Instructions
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| H A D | AMDGPUAsmGFX90a.rst | 964 VOP2 section in Instructions
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/ |
| H A D | literalv216_gfx10.txt | 144 # Packed VOP2
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| H A D | sdwa_gfx9.txt | 249 # VOP2
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3427 SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
4012 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
8987 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
8991 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
8995 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
9027 if (BasicInstType == SIInstrFlags::VOP2 && in cvtSDWA()
9079 case SIInstrFlags::VOP2: in cvtSDWA()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 380 ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) in printVOPDst()
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