Searched refs:VMLAVs (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 245 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply enumerator
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| H A D | ARMISelLowering.cpp | 1791 MAKE_CASE(ARMISD::VMLAVs) in getTargetNodeName()
13349 case ARMISD::VMLAVs: in TryDistrubutionADDVecReduce()
17010 return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B); in PerformVECREDUCE_ADDCombine()
17021 DAG.getNode(ARMISD::VMLAVs, dl, MVT::i32, A, B)); in PerformVECREDUCE_ADDCombine()
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| H A D | ARMInstrMVE.td | 1147 def ARMVMLAVs : SDNode<"ARMISD::VMLAVs", SDTVecReduce2>;
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