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Searched refs:VMLALVu (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h251 VMLALVu, // high 32-bit halves of the sum enumerator
H A DARMISelLowering.cpp1796 MAKE_CASE(ARMISD::VMLALVu) in getTargetNodeName()
13556 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N0, N1)) in PerformADDVecReduce()
13560 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0)) in PerformADDVecReduce()
16983 assert((Opcode == ARMISD::VMLALVs || Opcode == ARMISD::VMLALVu) && in PerformVECREDUCE_ADDCombine()
16985 bool IsUnsigned = Opcode == ARMISD::VMLALVu; in PerformVECREDUCE_ADDCombine()
17018 return Create64bitNode(ARMISD::VMLALVu, {A, B}); in PerformVECREDUCE_ADDCombine()
H A DARMInstrMVE.td1150 def ARMVMLALVu : SDNode<"ARMISD::VMLALVu", SDTVecReduce2L>;