Searched refs:VLSHR (Results 1 – 4 of 4) sorted by relevance
41 ; CHECK: [[VLSHR:%[0-9]+]]:_(<4 x s32>) = G_VLSHR [[COPY]], [[C]](s32)42 ; CHECK: $q0 = COPY [[VLSHR]](<4 x s32>)64 ; CHECK: [[VLSHR:%[0-9]+]]:_(<8 x s16>) = G_VLSHR [[COPY]], [[C]](s32)65 ; CHECK: $q0 = COPY [[VLSHR]](<8 x s16>)
195 VLSHR, enumerator
1905 case AArch64ISD::VLSHR: { in computeKnownBitsForTargetNode()2138 MAKE_CASE(AArch64ISD::VLSHR) in getTargetNodeName()10961 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()10966 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()10973 bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR; in tryLowerToSLI()11964 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; in LowerVectorSRA_SRL_SHL()17387 N->getOpcode() == AArch64ISD::VLSHR); in performVectorShiftCombine()19611 case AArch64ISD::VLSHR: in PerformDAGCombine()21916 if (ShiftR->getOpcode() != AArch64ISD::VLSHR) in SimplifyDemandedBitsForTargetNode()
611 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;