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Searched refs:VLD4DUP (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1388 (instregex "VLD4DUP(d|q)(8|16|32)$",
1389 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;
1393 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;
1395 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;
H A DARMISelLowering.h328 VLD4DUP, enumerator
H A DARMInstrNEON.td1601 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1602 class VLD4DUP<bits<4> op7_4, string Dt>
1612 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1613 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1614 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1621 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1622 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1623 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
H A DARMISelLowering.cpp1839 MAKE_CASE(ARMISD::VLD4DUP) in getTargetNodeName()
15733 case ARMISD::VLD4DUP: in TryCombineBaseUpdate()
16193 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
18657 case ARMISD::VLD4DUP: in PerformDAGCombine()
H A DARMISelDAGToDAG.cpp4367 case ARMISD::VLD4DUP: { in Select()