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Searched refs:VLD3DUP (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1341 (instregex "VLD3DUP(d|q)(8|16|32)$",
1342 "VLD3DUP(d|q)(8|16|32)Pseudo$")>;
1345 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>;
1347 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;
H A DARMISelLowering.h327 VLD3DUP, enumerator
H A DARMInstrNEON.td1544 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1545 class VLD3DUP<bits<4> op7_4, string Dt>
1555 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1556 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1557 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1564 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1565 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1566 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
H A DARMISelLowering.cpp1838 MAKE_CASE(ARMISD::VLD3DUP) in getTargetNodeName()
15729 case ARMISD::VLD3DUP: in TryCombineBaseUpdate()
16190 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
18656 case ARMISD::VLD3DUP: in PerformDAGCombine()
H A DARMISelDAGToDAG.cpp4359 case ARMISD::VLD3DUP: { in Select()