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Searched refs:VLD (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvbrd.ll6 ;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.
H A Dvld.ll6 ;;; We test VLD*rrl, VLD*irl, VLD*rrl_v, and VLD*irl_v instructions.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td87 // Read the unwritten lanes of the VLD's destination registers.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM4.td114 def : M4UnitL2I<(instregex "VLD")>;
H A DARMInstrInfo.td1313 // VLD/VST instructions and checking the alignment is not specified.
1324 // VLD/VST instructions and checking the alignment value.
1335 // VLD/VST instructions and checking the alignment value.
1346 // VLD/VST instructions and checking the alignment value.
1357 // for VLD/VST instructions and checking the alignment value.
1368 // encoding for VLD/VST instructions and checking the alignment value.
1378 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1399 // VLD-dup instruction and checking the alignment is not specified.
1409 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1431 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
[all …]
H A DARMScheduleA57.td145 "VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",
146 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
H A DARMISelLowering.cpp16179 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
16180 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
16184 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); in CombineVLDDUP()
16201 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); in CombineVLDDUP()
16202 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
16220 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
16221 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
16222 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
16227 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
16243 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
H A DARMInstrNEON.td555 // Classes for VLD* pseudo-instructions with multi-register operands.
1001 // Classes for VLD*LN pseudo-instructions with multi-register operands.
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td92 defm : VectorLoad<v256f64, i64, v256i1, "VGT", "VLD">;
93 defm : VectorLoad<v256i64, i64, v256i1, "VGT", "VLD">;
H A DVEInstrVec.td127 // Multiclass for VLD instructions
161 // Section 8.9.1 - VLD (Vector Load)
162 defm VLD : VLDm<"vld", 0x81, V64>;