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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfpconv.ll7 ;CHECK-VFP-LABEL: f1:
8 ;CHECK-VFP: vcvt.f32.f64
9 ;CHECK-VFP-SP-LABEL: f1:
19 ;CHECK-VFP-LABEL: f2:
20 ;CHECK-VFP: vcvt.f64.f32
31 ;CHECK-VFP-LABEL: f3:
43 ;CHECK-VFP-LABEL: f4:
55 ;CHECK-VFP-LABEL: f5:
67 ;CHECK-VFP-LABEL: f6:
79 ;CHECK-VFP-LABEL: f7:
[all …]
H A Dfp16-promote.ll13 ; CHECK-VFP: vadd.f32
30 ; CHECK-VFP: vsub.f32
47 ; CHECK-VFP: vmul.f32
208 ; CHECK-VFP: movmi
209 ; CHECK-VFP: str
668 ; CHECK-VFP: vmrs
688 ; CHECK-VFP: vmrs
867 ; CHECK-VFP: and
868 ; CHECK-VFP: mov
910 ; CHECK-VFP: mov
[all …]
H A Dfpvcvtr.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
2 ; RUN: llc -mtriple=thumbv7-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
11 ; CHECK-VFP: vcvtr.s32.f32 s0, s0
18 ; CHECK-VFP: vcvtr.u32.f32 s0, s0
25 ; CHECK-VFP: vcvtr.s32.f64 s0, d{{.*}}
32 ; CHECK-VFP: vcvtr.u32.f64 s0, d{{.*}}
H A Dfptosi-sat-scalar.ll562 ; VFP-NEXT: bx lr
672 ; VFP-NEXT: it lt
676 ; VFP-NEXT: it gt
789 ; VFP-NEXT: it lt
793 ; VFP-NEXT: it gt
797 ; VFP-NEXT: it vs
800 ; VFP-NEXT: it lt
804 ; VFP-NEXT: it gt
808 ; VFP-NEXT: it vs
971 ; VFP-NEXT: it lt
[all …]
H A Dfptoui-sat-scalar.ll434 ; VFP-NEXT: bx lr
596 ; VFP-NEXT: it lt
601 ; VFP-NEXT: it gt
604 ; VFP-NEXT: it lt
608 ; VFP-NEXT: it gt
729 ; VFP-NEXT: it lt
734 ; VFP-NEXT: it gt
738 ; VFP-NEXT: it lt
742 ; VFP-NEXT: it gt
746 ; VFP-NEXT: it lt
[all …]
H A Dfptoi-sat-store.ll62 ; VFP-LABEL: test_signed_i32_f32:
63 ; VFP: @ %bb.0:
64 ; VFP-NEXT: vmov s0, r1
65 ; VFP-NEXT: vcvt.s32.f32 s0, s0
66 ; VFP-NEXT: vstr s0, [r0]
67 ; VFP-NEXT: bx lr
197 ; VFP: @ %bb.0:
198 ; VFP-NEXT: vmov s0, r1
199 ; VFP-NEXT: vcvt.u32.f32 s0, s0
200 ; VFP-NEXT: vstr s0, [r0]
[all …]
H A Dno-fpu.ll4 …N: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
22 ; Likewise with VFP instructions.
29 ; NONEON-VFP: vmov
30 ; NONEON-VFP: vmul.f64
H A Dinlineasm-X-allocation.ll2 …iple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
16 ; VFP: FOO s0, s0
H A Dselect.ll4 ; RUN: | FileCheck %s --check-prefix=CHECK-VFP
67 ;CHECK-VFP-LABEL: f7:
68 ;CHECK-VFP: vmovmi
101 ; CHECK-VFP-LABEL: f9:
H A D2013-04-16-AAPCS-C5-vs-VFP.ll7 ;Co-Processor register candidates may be either in VFP or in stack, so after
8 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
H A Dvector-extend-narrow.ll23 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
52 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
H A D2013-04-16-AAPCS-C4-vs-VFP.ll6 ;Co-Processor register candidates may be either in VFP or in stack, so after
7 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
H A D2013-04-21-AAPCS-VA-C.1.cp.ll2 ;Note: There are no VFP CPRCs in a variadic procedure.
H A Dvfp-regs-dwarf.ll10 ; the layout of the VFP registers correctly. The fact that the numbers are
H A Dfpclamptosat.ll266 ; VFP-LABEL: stest_f32i32:
270 ; VFP-NEXT: bx lr
300 ; VFP-NEXT: bx lr
361 ; VFP-NEXT: bx lr
738 ; VFP-NEXT: bx lr
818 ; VFP-NEXT: bx lr
2404 ; VFP-NEXT: bx lr
2431 ; VFP-NEXT: bx lr
2483 ; VFP-NEXT: bx lr
2857 ; VFP-NEXT: bx lr
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dsingle-precision-fp.s10 @ CHECK-ERRORS: error: instruction requires: double precision VFP
12 @ CHECK-ERRORS: error: instruction requires: double precision VFP
14 @ CHECK-ERRORS: error: instruction requires: double precision VFP
16 @ CHECK-ERRORS: error: instruction requires: double precision VFP
18 @ CHECK-ERRORS: error: instruction requires: double precision VFP
29 @ CHECK-ERRORS: error: instruction requires: double precision VFP
31 @ CHECK-ERRORS: error: instruction requires: double precision VFP
33 @ CHECK-ERRORS: error: instruction requires: double precision VFP
35 @ CHECK-ERRORS: error: instruction requires: double precision VFP
37 @ CHECK-ERRORS: error: instruction requires: double precision VFP
[all …]
H A Dneon-mov-vfp.s1 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
2 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
14 @ VFP-DAG: error: instruction requires: NEON
15 @ VFP-DAG: error: instruction requires: NEON
26 @ VFP-DAG: error: instruction requires: NEON
27 @ VFP-DAG: error: instruction requires: NEON
H A Deh-directive-integrated-test.s19 @ restore the general-purpose and VFP registers.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td163 // Some single precision VFP instructions may be executed on both NEON and VFP
198 // Some single precision VFP instructions may be executed on both NEON and VFP
267 // VFP pipelines.
280 // VFP pipelines.
293 // VFP pipelines.
417 // VFP pipelines on A8.
442 // VFP pipelines on A8.
2218 // VFP pipelines.
2270 // VFP pipelines.
2322 // VFP pipelines.
[all …]
H A DARM.td63 /// Versions of the VFP flags restricted to single precision, or to
236 // Cyclone can zero VFP registers in 0 cycles.
238 // particularly effective at zeroing a VFP register.
292 // True if use a wider stride when allocating VFP registers.
304 // VFP register widths.
305 // True if splat a register between VFP and NEON instructions.
317 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
318 // True if VFP/NEON VMLA/VMLS have special RAW hazards.
323 // VFP to NEON, as an execution domain optimization.
346 // Some processors have a nonpipelined VFP coprocessor.
[all …]
H A DARMScheduleSwift.td602 // 4.2.34 Advanced SIMD and VFP, Floating Point
612 // 4.2.35 Advanced SIMD and VFP, Multiply
622 // 4.2.36 Advanced SIMD and VFP, Convert
625 // 4.2.37 Advanced SIMD and VFP, Move
652 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
673 // 4.2.39 Advanced SIMD and VFP, Load Single Element
676 // 4.2.40 Advanced SIMD and VFP, Store Single Element
679 // 4.2.41 Advanced SIMD and VFP, Load Multiple
680 // 4.2.42 Advanced SIMD and VFP, Store Multiple
1037 // 4.2.44 VFP, Divide and Square Root
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-legalize-load-store.mir127 ; Can't use the VFP support for unaligned operations, we need to use 32-bits
141 ; For word-aligned we can use VFP operations.
165 ; When we don't have VFP support, we need to use 32-bit operations.
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dfloat-intrinsics-double.ll3 …k %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-A…
128 ; VFP: lsrs [[REG:r[0-9]+]], {{r[0-9]+}}, #31
129 ; VFP: bfi {{r[0-9]+}}, [[REG]], #31, #1
H A Dfloat-intrinsics-float.ll4 … | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=VFP -check-prefix=FP-A…
124 ; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
125 ; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
/llvm-project-15.0.7/libunwind/src/
H A DUnwindRegistersSave.S788 @ however this is very hard to do for VFP registers because it is unknown
790 @ Instead, VFP registers are demand saved by logic external to __unw_getcontext.
863 @ VFP and iwMMX instructions are only available when compiling with the flags

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