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Searched refs:VF4 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dcast-induction.ll1 …-vectorize -force-vector-interleave=1 -force-vector-width=4 -S %s | FileCheck --check-prefix=VF4 %s
11 ; VF4-LABEL: @example12(
12 ; VF4-LABEL: vector.body:
13 ; VF4: [[VEC_IND:%.+]] = phi <4 x i32>
14 ; VF4: store <4 x i32> [[VEC_IND]]
15 ; VF4: middle.block:
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-strict-fadd-cost.ll4 ; RUN: -S 2>&1 | FileCheck %s --check-prefix=CHECK-VF4
10 ; RUN: -mcpu=neoverse-n2 -S 2>&1 | FileCheck %s --check-prefix=CHECK-VF4-CPU-NEOVERSE-N2
14 ; CHECK-VF4: Found an estimated cost of 16 for VF vscale x 4 For instruction: %add = fadd float %…
16 ; CHECK-VF4-CPU-NEOVERSE-N2: Found an estimated cost of 8 for VF vscale x 4 For instruction: %add…
37 ; CHECK-VF4: Found an estimated cost of 16 for VF vscale x 4 For instruction: %add = fadd double …
39 ; CHECK-VF4-CPU-NEOVERSE-N2: Found an estimated cost of 8 for VF vscale x 4 For instruction: %add…
H A Dstrict-fadd-cost.ll3 … -force-vector-width=4 -force-vector-interleave=1 -S 2>&1 | FileCheck %s --check-prefix=CHECK-VF4
9 ; CHECK-VF4: Found an estimated cost of 21 for VF 4 For instruction: %add = fadd float %0, %sum.07
31 ; CHECK-VF4: Found an estimated cost of 18 for VF 4 For instruction: %add = fadd double %0, %sum.…
52 ; CHECK-VF4: Found an estimated cost of 23 for VF 4 For instruction: %muladd = tail call float @l…
77 ; CHECK-VF4: Found an estimated cost of 22 for VF 4 For instruction: %muladd = tail call double @…
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/
H A Dslp-max-reg-size.ll3 …-max-vf=4 -slp-min-reg-size=32 -slp-max-reg-size=160 -S | FileCheck -check-prefix CHECK-VF4-160 %s
6 …p-max-vf=4 -slp-min-reg-size=32 -slp-max-reg-size=128 -S | FileCheck -check-prefix CHECK-VF4-128 %s
22 ; CHECK-VF4-160-LABEL: @foo(
23 ; CHECK-VF4-160-NEXT: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* bitcast ([8 x i32…
24 ; CHECK-VF4-160-NEXT: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32>* bitcast (i32* get…
25 ; CHECK-VF4-160-NEXT: ret void
39 ; CHECK-VF4-128-LABEL: @foo(
40 ; CHECK-VF4-128-NEXT: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* bitcast ([8 x i32…
41 ; CHECK-VF4-128-NEXT: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32>* bitcast (i32* get…
42 ; CHECK-VF4-128-NEXT: ret void
/llvm-project-15.0.7/clang/test/CXX/temp/temp.param/
H A Dp7.cpp41 typedef __attribute__((ext_vector_type(4))) float VF4; typedef
43 template<VF4> struct VectorFloat; // cxx17-error {{cannot have type 'VF4'}}
68 VF4 vf4;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td658 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
660 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
H A DRISCVInstrInfoVVLPatterns.td1010 defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4",
1012 defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4",
H A DRISCVInstrInfoVPseudos.td5068 defm : VPatUnaryV_VF<"int_riscv_vzext", "PseudoVZEXT", "VF4",
5074 defm : VPatUnaryV_VF<"int_riscv_vsext", "PseudoVSEXT", "VF4",
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td236 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td367 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,