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Searched refs:VDUPLANE (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h200 VDUPLANE, enumerator
H A DARMISelLowering.cpp1760 MAKE_CASE(ARMISD::VDUPLANE) in getTargetNodeName()
7941 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
7946 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
8385 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
8725 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
16208 if (User->getOpcode() != ARMISD::VDUPLANE || in CombineVLDDUP()
18616 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget); in PerformDAGCombine()
H A DARMInstrInfo.td258 // VDUPLANE can produce a quad-register result from a double-register source,
260 def ARMvduplane : SDNode<"ARMISD::VDUPLANE",