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Searched refs:VASHR (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizer-lowering-vashr-vlshr.mir18 ; CHECK: [[VASHR:%[0-9]+]]:_(<4 x s32>) = G_VASHR [[COPY]], [[C]](s32)
19 ; CHECK: $q0 = COPY [[VASHR]](<4 x s32>)
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h196 VASHR, enumerator
H A DAArch64ISelLowering.cpp1912 case AArch64ISD::VASHR: { in computeKnownBitsForTargetNode()
2139 MAKE_CASE(AArch64ISD::VASHR) in getTargetNodeName()
11964 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; in LowerVectorSRA_SRL_SHL()
13764 if (Shift.getOpcode() != AArch64ISD::VASHR || !Shift.hasOneUse() || in foldVectorXorShiftIntoCmp()
17386 assert(N->getOpcode() == AArch64ISD::VASHR || in performVectorShiftCombine()
19610 case AArch64ISD::VASHR: in PerformDAGCombine()
H A DAArch64InstrInfo.td610 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;