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Searched refs:VALU (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp60 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
67 return VALU; in getDelayType()
113 case VALU: in DelayInfo()
154 VALUNum += (Type == VALU); in advance()
166 TRANSNumVALU += (Type == VALU); in advance()
H A DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
155 let TSFlags{1} = VALU;
237 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
253 let VALU = 1;
461 let VALU = 1;
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
36 // Other quarter rate VALU instructions
68 // FIXME: Should there be a class for instructions which are VALU
69 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
113 def HWTransVALU : ProcResource<1> { // Transcendental VALU
H A DGCNHazardRecognizer.cpp865 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
868 if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) { in checkVALUHazards()
871 auto IsTransDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
878 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
895 auto IsShift16BitDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
915 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
944 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
958 if (VALU->readsRegister(AMDGPU::VCC, TRI)) { in checkVALUHazards()
966 switch (VALU->getOpcode()) { in checkVALUHazards()
969 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
[all …]
H A DGCNHazardRecognizer.h85 int checkVALUHazards(MachineInstr *VALU);
H A DAMDGPUIGroupLP.cpp214 VALU = 1u << 1, enumerator
331 if ((SBMask & SchedBarrierMasks::VALU) == SchedBarrierMasks::NONE && in getSchedGroupsFromMask()
H A DVOPInstructions.td50 let VALU = 1;
128 let VALU = 1;
163 let VALU = 1;
564 let VALU = 1;
585 let VALU = 1;
616 let VALU = 1;
775 let VALU = 1;
815 let VALU = 1;
855 let VALU = 1;
945 let VALU = 1;
H A DVOPDInstructions.td67 let VALU = 1;
H A DSIDefines.h30 VALU = 1 << 1, enumerator
H A DSIInstrInfo.h360 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
364 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
H A DVOP1Instructions.td56 let VALU = 1;
67 let VALU = 1;
221 let VALU = 1;
H A DSIInstructions.td642 let VALU = 1;
692 let VALU = 1;
708 let VALU = 1;
2177 // will be moved to the VALU.
2400 // Handle the VALU case.
H A DFLATInstructions.td103 let VALU = ps.VALU;
264 let VALU = 1;
426 let VALU = 1;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dinsert-delay-alu.mir67 # There's no encoding for VALU_DEP_5. A normal VALU instruction will have
198 # There's no need to encode the VALU depdendency because it will complete before
281 # dependency for the second mul has already guaranteed that a later VALU has
477 # No VALU delay across s_sendmsg_rtn because it waits for all outstanding VALU
496 # No VALU delay before or across FLAT because it waits for all outstanding VALU
516 # No VALU delay across an s_waitcnt_depctr that waits for all outstanding VALU
549 # Check if a VALU delay is added after writelane.
H A Dsplit-smrd.ll5 ; the VALU, we are also moving its users to the VALU.
H A Ddpp_combine.mir5 # bound_ctrl:1 is set, otherwise the result of DPP VALU op can be undefined.
68 # setting bound_ctrl:1 on for the combined DPP VALU op to make old undefined
75 # active src lane result - can combine with old = src1 of the VALU op.
76 # The VALU op should have the same masks as DPP mov as they select lanes
78 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
85 # active src lane result - can combine with old = src1 of the VALU op.
86 # The VALU op should have the same masks as DPP mov as they select
98 # for the unary VALU op
142 # range}) or src lane result - can combine with old = src1 of the VALU op
143 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
[all …]
H A Dsrem.ll32 ; FIXME: uniform i16 srem should not use VALU instructions
H A Dcarryout-selection.ll128 ; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC
325 ; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC
H A Duniform-cfg.ll119 ; be selected for the SALU and then later moved to the VALU.
143 ; be selected for the SALU and then later moved to the VALU.
H A Dbreak-smem-soft-clauses.mir275 # Regular VALU instruction breaks clause, no nop needed
H A Dvalu-i1.ll7 ; moved using VALU instructions
H A Dsalu-to-valu.ll53 ; Test moving an SMRD instruction to the VALU
89 ; Test moving an SMRD with an immediate offset to the VALU
H A Dand.ll61 ; can fold into the s_and_b32 and the VALU one is materialized
72 ; Just to stop future replacement of copy to vgpr + store with VALU op.
H A Dearly-if-convert.ll266 ; FIXME: Should be able to use VALU compare and select
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-ctpop.mir165 # SGPR->VGPR ctpop with VALU add
190 # Scalar ctpop with VALU add

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