Searched refs:VALIGN (Results 1 – 10 of 10) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 84 VALIGN, // Align two vectors (in Op0, Op1) to one that would have enumerator
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| H A D | HexagonISelLowering.cpp | 1917 case HexagonISD::VALIGN: return "HexagonISD::VALIGN"; in getTargetNodeName()
3087 SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy, in LowerUnalignedLoad()
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| H A D | HexagonISelDAGToDAG.cpp | 899 case HexagonISD::VALIGN: return SelectVAlign(N); in Select()
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| H A D | HexagonISelLoweringHVX.cpp | 772 HalfV = DAG.getNode(HexagonISD::VALIGN, dl, VecTy, in buildHvxVectorReg()
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| H A D | HexagonPatterns.td | 98 def HexagonVALIGN: SDNode<"HexagonISD::VALIGN", SDTVecVecIntOp>;
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 442 VALIGN, enumerator
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| H A D | X86InstrFragmentsSIMD.td | 379 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
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| H A D | X86SchedSkylakeServer.td | 1703 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
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| H A D | X86SchedIceLake.td | 1722 def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
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| H A D | X86ISelLowering.cpp | 5309 case X86ISD::VALIGN: in isTargetShuffle()
7705 case X86ISD::VALIGN: in getTargetShuffleMask()
13547 return DAG.getNode(X86ISD::VALIGN, DL, VT, Lo, Hi, in lowerShuffleAsVALIGN()
33607 NODE_NAME_CASE(VALIGN) in getTargetNodeName()
37715 Shuffle = X86ISD::VALIGN; in matchBinaryPermuteShuffle()
55134 case X86ISD::VALIGN: in PerformDAGCombine()
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