Searched refs:VADDVs (Results 1 – 3 of 3) sorted by relevance
233 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
1779 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()13347 case ARMISD::VADDVs: in TryDistrubutionADDVecReduce()17046 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()17055 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()17376 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
684 def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;