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/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A D2011-01-11-CC.ll11 ; V9: addcc
12 ; V9-NOT: subcc
13 ; V9: addx
28 ; V9: cmp
43 ; V9: cmp
57 ; V9: cmp
72 ;V9: fcmps
73 ;V9-NOT: nop
88 ;V9: fcmps
103 ;V9: fcmpd
[all …]
H A Dfp16-promote.ll29 ; V9: ! %bb.0:
33 ; V9-NEXT: ret
34 ; V9-NEXT: restore
59 ; V9: ! %bb.0:
64 ; V9-NEXT: ret
140 ; V9-NEXT: ret
191 ; V9-NEXT: ret
252 ; V9-NEXT: ret
310 ; V9-NEXT: ret
378 ; V9-NEXT: ret
[all …]
H A D2011-01-11-Call.ll14 ; V9-LABEL: test
15 ; V9: save %sp
16 ; V9: call foo
17 ; V9-NEXT: nop
18 ; V9: call bar
19 ; V9-NEXT: nop
20 ; V9: ret
21 ; V9-NEXT: restore
40 ; V9: save %sp
42 ; V9-NEXT: nop
[all …]
H A D2011-01-11-FrameAddr.ll15 ;V9-LABEL: frameaddr:
16 ;V9: save %sp, -96, %sp
17 ;V9: ret
39 ;V9-LABEL: frameaddr2:
40 ;V9: flushw
65 ;V9-LABEL: retaddr:
66 ;V9: mov %o7, {{.+}}
83 ;V9-LABEL: retaddr2:
84 ;V9: flushw
105 ;V9-LABEL: retaddr3:
[all …]
H A Dfloat.ll18 ; V9-LABEL: test_neg:
19 ; V9: fnegd %f0, %f0
42 ; V9: fabsd %f0, %f0
108 ; V9: fitos
109 ; V9: fstoi
151 ; V9: fitod
152 ; V9: fdtoi
193 ; V9: fdtos
194 ; V9: fstoi
236 ; V9-NOT: fitod
[all …]
H A Dctpop.ll2 ; RUN: llc < %s -march=sparc -mattr=+v9,+popc | FileCheck %s -check-prefix=V9
7 ; RUN: llc < %s -march=sparc -mcpu=niagara2 | FileCheck %s -check-prefix=V9
8 ; RUN: llc < %s -march=sparc -mcpu=niagara3 | FileCheck %s -check-prefix=V9
9 ; RUN: llc < %s -march=sparc -mcpu=niagara4 | FileCheck %s -check-prefix=V9
17 ; V9-LABEL: test
18 ; V9: srl %o0, 0, %o0
19 ; V9-NEXT: retl
20 ; V9-NEXT: popc %o0, %o0
H A Dsetjmp.ll2 ;RUN: llc -march=sparcv9 < %s | FileCheck %s --check-prefix=V9
19 ; V9-LABEL: foo
20 ; V9-DAG: st {{.+}}, [%i0]
21 ; V9-DAG: st {{.+}}, [%i0+4]
22 ; V9: call _setjmp
23 ; V9: ldx [%fp+{{.+}}], %[[R:[gilo][0-7]]]
24 ; V9: st %o0, [%[[R]]+{{.+}}]
H A D2009-08-28-PIC.ll2 ; RUN: llc -march=sparcv9 --relocation-model=pic < %s | FileCheck %s --check-prefix=V9
10 ; V9-LABEL: func
11 ; V9: _GLOBAL_OFFSET_TABLE_
/llvm-project-15.0.7/lld/test/ELF/
H A Demulation-sparc.s11 # V9: ElfHeader {
12 # V9-NEXT: Ident {
13 # V9-NEXT: Magic: (7F 45 4C 46)
14 # V9-NEXT: Class: 64-bit (0x2)
16 # V9-NEXT: FileVersion: 1
17 # V9-NEXT: OS/ABI: SystemV (0x0)
18 # V9-NEXT: ABIVersion: 0
20 # V9-NEXT: }
21 # V9-NEXT: Type: Executable (0x2)
22 # V9-NEXT: Machine: EM_SPARCV9 (0x2B)
[all …]
/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparcv9-instructions.s2 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
16 ! V9: subx %g2, %g1, %g3 ! encoding: [0x86,0x60,0x80,0x01]
41 ! V9: ld [%i0+%l6], %o2 ! encoding: [0xd4,0x06,0x00,0x16]
45 ! V9: ld [%i0+32], %o2 ! encoding: [0xd4,0x06,0x20,0x20]
49 ! V9: ld [%g1], %o2 ! encoding: [0xd4,0x00,0x40,0x00]
53 ! V9: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
96 ! V9: ldx [%g2+20], %fsr ! encoding: [0xc3,0x08,0xa0,0x14]
101 ! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
106 ! V9: stx %fsr, [%g2+20] ! encoding: [0xc3,0x28,0xa0,0x14]
111 ! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
[all …]
H A Dsparc-synthetic-instructions.s168 ! depending on whether targeting V8 or V9.
171 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
174 ! V9: sethi %hi(-1), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
176 ! V9: or %o1, %lo(-1), %o1 ! encoding: [0x92,0x12,0b011000AA,A]
181 ! V9: sethi %hi(-2), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
183 ! V9: or %o1, %lo(-2), %o1 ! encoding: [0x92,0x12,0b011000AA,A]
188 ! V9: sethi %hi(-16), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
190 ! V9: or %o1, %lo(-16), %o1 ! encoding: [0x92,0x12,0b011000AA,A]
195 ! V9: sethi %hi(-256), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
202 ! V9: sethi %hi(-4096), %o1 ! encoding: [0x13,0b00AAAAAA,A,A]
[all …]
H A Dsparc-asm-errors.s2 … llvm-mc %s -arch=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=V9
11 ! V9: unknown membar tag
15 ! V9: invalid membar mask number
21 ! V9: immediate shift value out of range
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DREADME.txt8 * When in V9 mode, register allocate %icc[0-3].
38 1) should be replaced with a brz in V9 mode.
40 * Same as above, but emit conditional move on register zero (p192) in V9
49 * Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dparallel-loop-tiling.mlir28 // CHECK: [[V9:%.*]] = arith.addi [[V7]], [[V3]] : index
30 // CHECK: [[V11:%.*]] = memref.load [[ARG8]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
31 // CHECK: [[V12:%.*]] = memref.load [[ARG9]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
33 // CHECK: memref.store [[V13]], [[ARG10]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
95 // CHECK: scf.parallel ([[V8:%.*]], [[V9:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V3]], [[…
97 // CHECK: = arith.addi [[V9]], [[V6]] : index
H A Dparallel-loop-tiling-inbound-check.mlir25 // CHECK: [[V9:%.*]] = arith.addi [[V7]], [[V3]] : index
37 // CHECK: [[V19:%.*]] = memref.load [[ARG8]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
38 // CHECK: [[V20:%.*]] = memref.load [[ARG9]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
40 // CHECK: memref.store [[V21]], [[ARG10]]{{\[}}[[V9]], [[V10]]] : memref<?x?xf32>
103 // CHECK: scf.parallel ([[V8:%.*]], [[V9:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V3]], [[…
105 // CHECK: = arith.addi [[V9]], [[V6]] : index
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dweak-in-c-struct.m72 // ARM64: %[[V9:.*]] = getelementptr inbounds i8, i8* %[[V8]], i64 8
73 // ARM64: %[[V10:.*]] = bitcast i8* %[[V9]] to i8**
98 // ARM64: %[[V9:.*]] = getelementptr inbounds i8, i8* %[[V8]], i64 8
99 // ARM64: %[[V10:.*]] = bitcast i8* %[[V9]] to i8**
126 // ARM64: %[[V9:.*]] = getelementptr inbounds i8, i8* %[[V8]], i64 8
127 // ARM64: %[[V10:.*]] = bitcast i8* %[[V9]] to i8**
153 // ARM64: %[[V9:.*]] = getelementptr inbounds i8, i8* %[[V8]], i64 8
154 // ARM64: %[[V10:.*]] = bitcast i8* %[[V9]] to i8**
H A Dstrong-in-c-struct.m198 // CHECK: store i8* %[[V9]], i8** %[[V4]], align 8
226 // CHECK: %[[V9:.*]] = bitcast i8* %[[V8]] to i8**
227 // CHECK: %[[V10:.*]] = load i8*, i8** %[[V9]], align 8
309 // CHECK: %[[V9:.*]] = load i8*, i8** %[[V4]], align 8
311 // CHECK: call void @llvm.objc.release(i8* %[[V9]])
357 // CHECK: %[[V9:.*]] = bitcast i8* %[[V8]] to i8**
425 // CHECK: %[[V9:.*]] = bitcast i8* %[[V8]] to i8**
627 // CHECK: %[[V7]] = bitcast i8* %[[V9]] to i8**
699 // CHECK: %[[V9:.*]] = bitcast i8* %[[V8]] to i8**
701 // CHECK: %[[V11:.*]] = bitcast i8** %[[V9]] to i16*
[all …]
H A Dnontrivial-c-struct-exception.m28 // CHECK: %[[V9:.*]] = bitcast %[[STRUCT_STRONG]]* %[[AGG_TMP]] to i8**{{.*}}, !dbg [[ARTIFICIAL_LO…
29 // CHECK: call void @__destructor_8_s8(i8** %[[V9]]){{.*}}, !dbg [[ARTIFICIAL_LOC_1]]
H A Dos_log.m39 // CHECK: %[[V9:.*]] = load i8*, i8** %[[A_ADDR]], align 8
40 // CHECK: %[[V10:.*]] = ptrtoint i8* %[[V9]] to i64
89 // CHECK-O2: %[[V9:.*]] = load i8*, i8** %[[OS_LOG_ARG]], align 8
90 // CHECK-O2: call void @llvm.objc.release(i8* %[[V9]])
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/fuchsia/
H A Dmultiple-inheritance.cpp113 struct V9 : virtual Base5 { virtual void f(); }; struct
115 struct D6 : V9, V10 {};
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td96 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
98 // Vector types returned as "direct" go into V2 .. V9; note that only the
102 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
153 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
156 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
237 V8, V9, V10, V11, V12, V13]>>>,
242 V8, V9, V10, V11, V12, V13]>>>,
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dliveness_chains.ll45 ; CHECK-NEXT: [[V9:%.*]] = add i32 [[V7]], [[V8]]
46 ; CHECK-NEXT: ret i32 [[V9]]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dsmlad11.ll12 ; CHECK: [[V9:%[0-9]+]] = load i32, i32* [[V8]], align 2
13 ; CHECK: [[ACC:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
/llvm-project-15.0.7/llvm/test/Transforms/MergeICmps/X86/
H A Dentry-block-shuffled-2.ll34 ; CHECK-NEXT: [[V9:%.*]] = phi i1 [ [[TMP7]], [[LAND_RHS1]] ], [ false, %"land.lhs.true+entry" ]
35 ; CHECK-NEXT: ret i1 [[V9]]
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Darc-blocks.mm73 // CHECK: %[[V9:.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %[[STRUCT_BLOCK_DESCRIPTOR]]*,…
75 // CHECK: %[[BLOCKCOPY_SRC2:.*]] = load i8*, i8** %[[V9]], align 8
235 // CHECK-NOHEAP: %[[V9:.*]] = load void ()*, void ()** %[[B0]], align 8
236 // CHECK-NOHEAP: %[[V10:.*]] = bitcast void ()* %[[V9]] to i8*
280 // CHECK-NOHEAP: %[[V9:.*]] = load void ()*, void ()** %[[B0]], align 8
281 // CHECK-NOHEAP: %[[V10:.*]] = bitcast void ()* %[[V9]] to i8*

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