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/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsHexagonDep.def12 // V5 Scalar Instructions.
14 TARGET_BUILTIN(__builtin_HEXAGON_A2_abs, "ii", "", V5)
15 TARGET_BUILTIN(__builtin_HEXAGON_A2_absp, "LLiLLi", "", V5)
16 TARGET_BUILTIN(__builtin_HEXAGON_A2_abssat, "ii", "", V5)
17 TARGET_BUILTIN(__builtin_HEXAGON_A2_add, "iii", "", V5)
35 TARGET_BUILTIN(__builtin_HEXAGON_A2_and, "iii", "", V5)
38 TARGET_BUILTIN(__builtin_HEXAGON_A2_aslh, "ii", "", V5)
39 TARGET_BUILTIN(__builtin_HEXAGON_A2_asrh, "ii", "", V5)
54 TARGET_BUILTIN(__builtin_HEXAGON_A2_neg, "ii", "", V5)
57 TARGET_BUILTIN(__builtin_HEXAGON_A2_not, "ii", "", V5)
[all …]
H A DBuiltinsHexagon.def36 #pragma push_macro("V5")
37 #define V5 "v5|" V55
57 TARGET_BUILTIN(__builtin_SI_to_SXTHI_asrh, "ii", "", V5)
59 TARGET_BUILTIN(__builtin_brev_ldw, "v*i*Ci*iC", "", V5)
60 TARGET_BUILTIN(__builtin_brev_ldh, "v*s*Cs*iC", "", V5)
71 TARGET_BUILTIN(__builtin_brev_stw, "i*Ci*iiC", "", V5)
72 TARGET_BUILTIN(__builtin_brev_sth, "s*Cs*iiC", "", V5)
73 TARGET_BUILTIN(__builtin_brev_sthhi, "s*Cs*iiC", "", V5)
74 TARGET_BUILTIN(__builtin_brev_stb, "c*Cc*iiC", "", V5)
76 TARGET_BUILTIN(__builtin_circ_stw, "i*i*iiIi", "", V5)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dldr_ext.ll1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
7 ; V5: ldrb
16 ; V5: ldrh
25 ; V5: ldrb
26 ; V5: lsls
27 ; V5: asrs
37 ; V5: ldrh
38 ; V5: lsls
39 ; V5: asrs
49 ; V5: movs r0, #0
[all …]
/llvm-project-15.0.7/llvm/unittests/Support/
H A DAlignOfTest.cpp69 struct V5 : V4, V3 { double z; argument
70 ~V5() override;
76 struct V8 : V5, virtual V6, V7 { double zz;
86 V5::~V5() {} in ~V5()
169 EXPECT_EQ(alignof(V5), alignof(AlignedCharArrayUnion<V5>)); in TEST()
234 EXPECT_EQ(sizeof(V5), sizeof(AlignedCharArrayUnion<V5>)); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A DPhiEliminate2.ll13 %V5 = sext i16 %V3 to i32
16 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ]
22 ; CHECK-NEXT: %V5 = sext i16 %V3 to i32
24 ; CHECK-NEXT: %V6 = select i1 %C, i32 %V4, i32 %V5, !prof !0, !unpredictable !1
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dos_log.m34 // CHECK: %[[V5:.*]] = bitcast %{{.*}}* %[[V4]] to i8*
35 // CHECK: %[[V6:.*]] = call i8* @llvm.objc.retain(i8* %[[V5]])
81 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
82 // CHECK: store i8* %[[V5]], i8** %[[OS_LOG_ARG]], align 8
83 // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64
88 // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V5]])
105 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
106 // CHECK: store i8* %[[V5]], i8** %[[OS_LOG_ARG]], align 8
107 // CHECK: %[[V6:.*]] = ptrtoint i8* %[[V5]] to i64
121 // CHECK-O2: call void (...) @llvm.objc.clang.arc.use(i8* %[[V5]])
H A Dstrong-in-c-struct.m193 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
223 // CHECK: %[[V6:.*]] = bitcast i8* %[[V5]] to i8**
246 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
278 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
304 // CHECK: %[[V5:.*]] = bitcast i8** %[[V1]] to i8*
354 // CHECK: %[[V6:.*]] = bitcast i8* %[[V5]] to i8**
375 // CHECK: %[[V5:.*]] = bitcast i8* %[[V4]] to i8**
397 // CHECK: %[[V5:.*]] = bitcast i8* %[[V4]] to i8**
422 // CHECK: %[[V6:.*]] = bitcast i8* %[[V5]] to i8**
474 // CHECK: ret [2 x i64] %[[V5]]
[all …]
H A Dweak-in-c-struct.m68 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
69 // ARM64: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 8
94 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
95 // ARM64: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 8
122 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
123 // ARM64: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 8
149 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
150 // ARM64: %[[V6:.*]] = getelementptr inbounds i8, i8* %[[V5]], i64 8
H A Dobjc-dispatch-null-check.m22 // CHECK: %[[V5:.*]] = bitcast i8* %[[MSGSEND_FN]] to void (i8*, i8*, i8*)*
25 // CHECK: call void %[[V5]]({{.*}}, i8* %[[V6]])
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepArch.h19 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68, V69 }; enumerator
23 .Case("generic", Hexagon::ArchEnum::V5) in getCpu()
24 .Case("hexagonv5", Hexagon::ArchEnum::V5) in getCpu()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Ddebugtrap.ll5 ; RUN: llc < %s -mtriple=armv5 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V5 %s
7 ; RUN: llc < %s -mtriple=thumbv5 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V5 %s
16 ; V5-NEXT: bkpt #0
H A Dpr18364-movw.ll1 ; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
9 ; V5-NOT: movw
25 ; V5-NOT: movw
H A DMachO-subtypes.ll7 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
9 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
11 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
13 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
15 ; RUN: | llvm-readobj --file-headers - | FileCheck %s --check-prefix=CHECK-V5
61 ; CHECK-V5: CpuSubType: CPU_SUBTYPE_ARM_V5 (0x7)
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dcase-insen-reg-names.s4 fadd V0.2d, V5.2d, V6.2d
5 fadd v0.2d, V5.2d, v6.2d
/llvm-project-15.0.7/mlir/test/Target/Cpp/
H A Dconst.mlir19 // CPP-DEFAULT-NEXT: char [[V5:[^ ]*]] = CHAR_MIN;
27 // CPP-DECLTOP-NEXT: char [[V5:[^ ]*]];
33 // CPP-DECLTOP-NEXT: [[V5]] = CHAR_MIN;
H A Dif.mlir75 // CPP-DEFAULT-NEXT: int32_t [[V5:[^ ]*]] = func_true_1([[V1]]);
77 // CPP-DEFAULT-NEXT: [[V3]] = [[V5]];
91 // CPP-DECLTOP-NEXT: int32_t [[V5:[^ ]*]];
97 // CPP-DECLTOP-NEXT: [[V5]] = func_true_1([[V1]]);
99 // CPP-DECLTOP-NEXT: [[V3]] = [[V5]];
H A Dcast.mlir9 // CHECK-NEXT: int64_t [[V5:[^ ]*]] = (uint64_t) [[V0:[^ ]*]]
14 // CHECK-NEXT: double [[V5:[^ ]*]] = (double) [[V0:[^ ]*]]
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dparallel-loop-tiling.mlir25 // CHECK: [[V5:%.*]] = affine.min #map([[V1]], [[ARG3]], [[V3]])
27 // CHECK: scf.parallel ([[V7:%.*]], [[V8:%.*]]) = ([[C0]], [[C0]]) to ([[V5]], [[V6]]) …
61 // CHECK: scf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V1]], [[V2…
62 // CHECK: = arith.addi [[V5]], [[V3]] : index
93 // CHECK: scf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) …
96 // CHECK: = arith.addi [[V8]], [[V5]] : index
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dmacro_vaopt_check.cpp25 #define V5(...) __VA_OPT__(__VA_OPT__()) macro
26 #undef V5
/llvm-project-15.0.7/clang/test/PCH/
H A Dnon-trivial-c-compound-literal.m22 // CHECK: %[[V5:.*]] = bitcast %[[STRUCT_S]]* %[[_COMPOUNDLITERAL]] to i8**
23 // CHECK: call void @__destructor_8_s0(i8** %[[V5]])
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Delf-flags.s1 …gonv5 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V5 %s
6 # CHECK-V5: Flags: 0x4
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dpr34349.ll9 ; CHECK-NEXT: [[V5:%.*]] = lshr i16 [[V4]], 8
10 ; CHECK-NEXT: [[V6:%.*]] = trunc i16 [[V5]] to i8
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-code-object-version.hip57 // RUN: %s 2>&1 | FileCheck -check-prefix=V5 %s
59 // V5: "-mcode-object-version=5"
60 // V5: "-mllvm" "--amdhsa-code-object-version=5"
61 // V5: "-targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx906"
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECallingConv.td107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dsink-common-code-into-unreachable.ll25 ; CHECK-NEXT: [[V5:%.*]] = add i32 [[V4]], [[C:%.*]]
27 ; CHECK-NEXT: [[R7:%.*]] = add i32 [[V5]], [[V6]]
78 ; CHECK-NEXT: [[V5:%.*]] = add i32 [[V4]], [[C]]
80 ; CHECK-NEXT: [[R7:%.*]] = add i32 [[V5]], [[V6]]

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