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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Difcvt3.ll16 ; CHECK-V4-CMP-LABEL: t1:
17 ; CHECK-V4-CMP: @ %bb.0:
18 ; CHECK-V4-CMP-NEXT: cmp r2, #7
19 ; CHECK-V4-CMP-NEXT: cmpne r2, #1
23 ; CHECK-V4-CMP-NEXT: bx lr
25 ; CHECK-V4-BX-LABEL: t1:
26 ; CHECK-V4-BX: @ %bb.0:
27 ; CHECK-V4-BX-NEXT: cmp r2, #7
28 ; CHECK-V4-BX-NEXT: cmpne r2, #1
29 ; CHECK-V4-BX-NEXT: addne r0, r1, r0
[all …]
H A Dmulhi.ll2 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=V4
9 ; V4-LABEL: smulhi:
10 ; V4: smull
26 ; V4-LABEL: umulhi:
27 ; V4: umull
44 ; V4-LABEL: t3:
45 ; V4: smull
H A Dsmml.ll19 ; CHECK-V4-LABEL: Test0:
20 ; CHECK-V4: @ %bb.0: @ %entry
22 ; CHECK-V4-NEXT: sub r0, r0, r12
23 ; CHECK-V4-NEXT: mov pc, lr
84 ; CHECK-V4-LABEL: Test1:
89 ; CHECK-V4-NEXT: mov pc, lr
151 ; CHECK-V4: @ %bb.0:
157 ; CHECK-V4-NEXT: movge r0, #42
158 ; CHECK-V4-NEXT: movlt r0, #56
159 ; CHECK-V4-NEXT: bl opaque
[all …]
H A D2010-03-18-ldm-rtrn.ll1 ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=V4
10 ; V4: pop
11 ; V4-NEXT: mov pc, lr
H A Ddebugtrap.ll4 ; RUN: llc < %s -mtriple=armv4 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V4 %s
6 ; RUN: llc < %s -mtriple=thumbv4 -O0 -filetype=asm | FileCheck --check-prefixes=CHECK,V4 %s
15 ; V4-NEXT: udf #254
/llvm-project-15.0.7/llvm/test/Object/
H A Dnm-tapi.test11 RUN: | FileCheck %s -check-prefix V4
14 RUN: | FileCheck %s -check-prefix V4-WATCH
54 V4: /u/l/libFoo.dylib (for architecture i386):
55 V4-NEXT: 00000000 S _sym1
56 V4-NEXT: 00000000 W _sym2
57 V4-NEXT: 00000000 S _sym3
58 V4-NEXT: 00000000 S _sym4
60 V4-NEXT: 0000000000000000 S _sym3
61 V4-NEXT: 0000000000000000 S _sym4
64 V4-WATCH-NEXT: 00000000 S _sym1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dtrap-abis.ll39 ; NOHSA-TRAP-GFX900-V4-LABEL: trap:
40 ; NOHSA-TRAP-GFX900-V4: ; %bb.0:
47 ; NOHSA-TRAP-GFX900-V4-NEXT: s_endpgm
141 ; HSA-TRAP-GFX803-V4-LABEL: trap:
142 ; HSA-TRAP-GFX803-V4: ; %bb.0:
151 ; HSA-TRAP-GFX803-V4-NEXT: s_trap 2
243 ; HSA-TRAP-GFX900-V4-LABEL: trap:
244 ; HSA-TRAP-GFX900-V4: ; %bb.0:
341 ; HSA-NOTRAP-GFX900-V4-LABEL: trap:
932 ; HSA-TRAP-GFX803-V4: ; %bb.0:
[all …]
/llvm-project-15.0.7/llvm/lib/Support/
H A Dxxhash.cpp82 uint64_t V4 = Seed - PRIME64_1; in xxHash64() local
91 V4 = round(V4, endian::read64le(P)); in xxHash64()
95 H64 = rotl64(V1, 1) + rotl64(V2, 7) + rotl64(V3, 12) + rotl64(V4, 18); in xxHash64()
99 H64 = mergeRound(H64, V4); in xxHash64()
/llvm-project-15.0.7/llvm/unittests/Support/
H A DAlignOfTest.cpp66 struct V4 : virtual V2 { int y; argument
67 ~V4() override;
69 struct V5 : V4, V3 { double z;
85 V4::~V4() {} in ~V4()
168 EXPECT_EQ(alignof(V4), alignof(AlignedCharArrayUnion<V4>)); in TEST()
233 EXPECT_EQ(sizeof(V4), sizeof(AlignedCharArrayUnion<V4>)); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A DPhiEliminate2.ll10 %V4 = or i32 %V2, %V1
16 %V6 = phi i32 [ %V5, %else ], [ %V4, %then ]
23 ; CHECK-NEXT: %V4 = or i32 %V2, %V1
24 ; CHECK-NEXT: %V6 = select i1 %C, i32 %V4, i32 %V5, !prof !0, !unpredictable !1
/llvm-project-15.0.7/mlir/test/Target/Cpp/
H A Dstdops.mlir18 // CPP-DEFAULT-NEXT: Tensor<size_t, 2> [[V4:[^ ]*]] = {0, 1};
26 // CPP-DECLTOP-NEXT: Tensor<size_t, 2> [[V4:[^ ]*]];
32 // CPP-DECLTOP-NEXT: [[V4]] = {0, 1};
63 // CPP-DEFAULT-NEXT: float [[V4:[^ ]*]];
64 // CPP-DEFAULT-NEXT: std::tie([[V3]], [[V4]]) = two_results();
71 // CPP-DECLTOP-NEXT: float [[V4:[^ ]*]];
74 // CPP-DECLTOP-NEXT: std::tie([[V3]], [[V4]]) = two_results();
H A Dif.mlir73 // CPP-DEFAULT-NEXT: double [[V4:[^ ]*]];
78 // CPP-DEFAULT-NEXT: [[V4]] = [[V6]];
83 // CPP-DEFAULT-NEXT: [[V4]] = [[V8]];
90 // CPP-DECLTOP-NEXT: double [[V4:[^ ]*]];
100 // CPP-DECLTOP-NEXT: [[V4]] = [[V6]];
105 // CPP-DECLTOP-NEXT: [[V4]] = [[V8]];
H A Dconst.mlir18 // CPP-DEFAULT-NEXT: uint8_t [[V4:[^ ]*]] = 255;
26 // CPP-DECLTOP-NEXT: uint8_t [[V4:[^ ]*]];
32 // CPP-DECLTOP-NEXT: [[V4]] = 255;
H A Dvariable.mlir19 // CPP-DEFAULT-NEXT: uint8_t [[V4:[^ ]*]] = 255;
28 // CPP-DECLTOP-NEXT: uint8_t [[V4:[^ ]*]];
35 // CPP-DECLTOP-NEXT: [[V4]] = 255;
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dos_log.m29 // CHECK-O2: %[[V4:.*]] = call %{{.*}}* @GenString() [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.ob…
33 // CHECK-O0: %[[V4:.*]] = bitcast i8* %[[V3]] to %{{.*}}*
34 // CHECK: %[[V5:.*]] = bitcast %{{.*}}* %[[V4]] to i8*
42 // CHECK: %[[V11:.*]] = bitcast %{{.*}}* %[[V4]] to i8*
80 // CHECK: %[[V4:.*]] = bitcast %{{.*}}* %[[V3]] to i8*
81 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
102 // CHECK-O2: %[[V4:.*]] = call {{.*}} @objc_msgSend{{.*}} [ "clang.arc.attachedcall"(i8* (i8*)* @ll…
104 // CHECK-O0: %[[V4:.*]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* %[[CALL]])
105 // CHECK: %[[V5:.*]] = call i8* @llvm.objc.retain(i8* %[[V4]])
116 // CHECK: call void @llvm.objc.release(i8* %[[V4]])
H A Dstrong-in-c-struct.m130 // CHECK: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
141 // CHECK: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
192 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
198 // CHECK: store i8* %[[V9]], i8** %[[V4]], align 8
221 // CHECK: %[[V4:.*]] = bitcast i8** %[[V0]] to i8*
245 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
277 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
283 // CHECK: store i8* %[[V8]], i8** %[[V4]], align 8
303 // CHECK: %[[V4:.*]] = bitcast i8* %[[V3]] to i8**
310 // CHECK: store i8* %[[V8]], i8** %[[V4]], align 8
[all …]
H A Dweak-in-c-struct.m33 // ARM64: %[[V4:.*]] = bitcast i8** %[[V3]] to i8*
34 // ARM64: call void @llvm.memset.p0i8.i64(i8* align 8 %[[V4]], i8 0, i64 8, i1 false)
66 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
67 // ARM64: store i32 %[[V4]], i32* %[[V2]], align 8
92 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
93 // ARM64: store i32 %[[V4]], i32* %[[V2]], align 8
120 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
121 // ARM64: store i32 %[[V4]], i32* %[[V2]], align 8
147 // ARM64: %[[V4:.*]] = load i32, i32* %[[V3]], align 8
148 // ARM64: store i32 %[[V4]], i32* %[[V2]], align 8
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dparallel-loop-tiling.mlir24 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[ARG1]], [[ARG2]]) to ([[ARG3]], [[AR…
26 // CHECK: [[V6:%.*]] = affine.min #map([[V2]], [[ARG4]], [[V4]])
29 // CHECK: [[V10:%.*]] = arith.addi [[V8]], [[V4]] : index
60 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[C0]], [[C0]]) to ([[C22]], [[C24]]) …
63 // CHECK: = arith.addi [[V6]], [[V4]] : index
92 // CHECK: [[V4:%.*]] = arith.muli [[C1]], [[C4]] : index
93 …cf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) step ([[V3]], [[V4]]) {
94 // CHECK: [[V7:%.*]] = affine.min #map([[V4]], [[C2]], [[V6]])
H A Dparallel-loop-tiling-inbound-check.mlir23 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[ARG1]], [[ARG2]]) to ([[ARG3]], [[AR…
26 // CHECK: [[V10:%.*]] = arith.addi [[V8]], [[V4]] : index
33 // CHECK: [[V16:%.*]] = arith.addi [[V15]], [[V4]] : index
68 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[C0]], [[C0]]) to ([[C22]], [[C24]]) …
72 // CHECK: = arith.addi [[V6]], [[V4]] : index
101 // CHECK: [[V4:%.*]] = arith.muli [[C1]], [[C4]] : index
102 …cf.parallel ([[V5:%.*]], [[V6:%.*]]) = ([[C0]], [[C0]]) to ([[C2]], [[C2]]) step ([[V3]], [[V4]]) {
103 …scf.parallel ([[V8:%.*]], [[V9:%.*]]) = ([[C0_1]], [[C0_1]]) to ([[V3]], [[V4]]) step ([[C1]], [[C…
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dreduction-transpose.ll42 ; SSE2-NEXT: [[VECEXT24:%.*]] = extractelement <4 x i32> [[V4]], i64 1
43 ; SSE2-NEXT: [[VECEXT26:%.*]] = extractelement <4 x i32> [[V4]], i64 2
44 ; SSE2-NEXT: [[VECEXT28:%.*]] = extractelement <4 x i32> [[V4]], i64 3
94 ; AVX-NEXT: [[VECEXT24:%.*]] = extractelement <4 x i32> [[V4]], i64 1
95 ; AVX-NEXT: [[VECEXT26:%.*]] = extractelement <4 x i32> [[V4]], i64 2
96 ; AVX-NEXT: [[VECEXT28:%.*]] = extractelement <4 x i32> [[V4]], i64 3
164 ; SSE2-NEXT: [[VECEXT12:%.*]] = extractelement <4 x i32> [[V4]], i64 1
168 ; SSE2-NEXT: [[VECEXT20:%.*]] = extractelement <4 x i32> [[V4]], i64 2
214 ; AVX-NEXT: [[VECEXT12:%.*]] = extractelement <4 x i32> [[V4]], i64 1
218 ; AVX-NEXT: [[VECEXT20:%.*]] = extractelement <4 x i32> [[V4]], i64 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dwiden-ext.ll21 ; CHECK: v[[V3:[0-9]+]]:[[V4:[0-9]+]].w = vunpack(v[[V2]].h)
22 ; CHECK: vmem(r1+#0) = v[[V4]]
46 ; CHECK: v[[V3:[0-9]+]]:[[V4:[0-9]+]].w = vunpack(v[[V2]].h)
47 ; CHECK-DAG: vmem(r1+#0) = v[[V4]]
89 ; CHECK: v[[V3:[0-9]+]]:[[V4:[0-9]+]].w = vunpack(v[[V2]].h)
90 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V4]]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-smin.ll12 ; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector…
20 ; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vecto…
28 ; MVE-NEXT: Cost Model: Found an estimated cost of 212 for instruction: %V4 = call i64 @llvm.vecto…
35 %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
44 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector…
67 %V4 = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef)
103 %V4 = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> undef)
114 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.…
124 ; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector…
134 ; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector…
[all …]
H A Dreduce-umax.ll12 ; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector…
20 ; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vecto…
28 ; MVE-NEXT: Cost Model: Found an estimated cost of 212 for instruction: %V4 = call i64 @llvm.vecto…
35 %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
44 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector…
67 %V4 = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> undef)
103 %V4 = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> undef)
114 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.…
124 ; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector…
134 ; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector…
[all …]
H A Dreduce-smax.ll12 ; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector…
20 ; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vecto…
28 ; MVE-NEXT: Cost Model: Found an estimated cost of 212 for instruction: %V4 = call i64 @llvm.vecto…
35 %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
44 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector…
67 %V4 = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> undef)
103 %V4 = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> undef)
114 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.…
124 ; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector…
134 ; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector…
[all …]
H A Dreduce-umin.ll12 ; V8M-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector…
20 ; NEON-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V4 = call i64 @llvm.vecto…
28 ; MVE-NEXT: Cost Model: Found an estimated cost of 212 for instruction: %V4 = call i64 @llvm.vecto…
35 %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
44 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i32 @llvm.vector…
67 %V4 = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> undef)
103 %V4 = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> undef)
114 ; V8M-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4 = call i8 @llvm.vector.…
124 ; NEON-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %V4 = call i8 @llvm.vector…
134 ; MVE-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V4 = call i8 @llvm.vector…
[all …]

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