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Searched refs:Upl (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dinline-asm-constraints-bad-sve.ll36 …%2 = call half asm "fminv ${0:h}, $1, $2.h", "=r,@3Upl,w"(<vscale x 16 x i1> %0, <vscale x 8 x hal…
H A Daarch64-sve-asm.ll57 …%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 …
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp8976 Upl, enumerator
8986 P = PredicateConstraint::Upl; in parsePredicateConstraint()
9114 bool restricted = (PC == PredicateConstraint::Upl); in getRegForInlineAsmConstraint()
/llvm-project-15.0.7/llvm/docs/
H A DLangRef.rst4776 - ``Upl``: One of the low eight SVE predicate registers (P0 to P7)