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Searched refs:UndefReg (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anon9082dfe70111::RegSeqInfo
61 UndefReg.push_back(Chan); in RegSeqInfo()
161 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
164 It.second, Untouched->UndefReg[CurrentUndexIdx++])); in tryMergeVector()
191 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
229 RSI->UndefReg = UpdatedUndef; in RebuildVector()
295 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
310 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
H A DSIOptimizeVGPRLiveRange.cpp508 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
515 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeLiveRange()
551 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
568 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeWaterfallLiveRange()
H A DSILowerI1Copies.cpp428 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local
430 UndefReg); in insertUndefLaneMask()
431 return UndefReg; in insertUndefLaneMask()
H A DAMDGPUInstructionSelector.cpp2091 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2092 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2096 .addReg(UndefReg) in selectG_SZA_EXT()
2150 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2153 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2157 .addReg(UndefReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp11821 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
11824 UndefReg, Src0, SDValue()); in PostISelFolding()
11838 Src0 = UndefReg; in PostISelFolding()
11839 Src1 = UndefReg; in PostISelFolding()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp543 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
547 .addReg(UndefReg) in adjustCallSequence()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp362 Register UndefReg; in matchCombineShuffleVector() local
366 if (!UndefReg) { in matchCombineShuffleVector()
368 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
370 Ops.push_back(UndefReg); in matchCombineShuffleVector()
2605 Register UndefReg; in applyCombineInsertVecElts() local
2607 if (UndefReg) in applyCombineInsertVecElts()
2608 return UndefReg; in applyCombineInsertVecElts()
2610 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2611 return UndefReg; in applyCombineInsertVecElts()
H A DLegalizerHelper.cpp1590 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
1592 Unmerges.push_back(UndefReg); in widenScalarMergeValues()