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Searched refs:UZP2 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-neon-mul-div-cte.ll8 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).16b]], [[SMULL]].16b, [[SMULL2]].16b
9 ; CHECK-NEXT: sshr [[SSHR:(v[0-9]+.16b)]], [[UZP2]], #2
21 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).8h]], [[SMULL]].8h, [[SMULL2]].8h
22 ; CHECK-NEXT: add [[ADD:(v[0-9]+).8h]], [[UZP2]], v0.8h
36 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).4s]], [[SMULL]].4s, [[SMULL2]].4s
37 ; CHECK-NEXT: sshr [[SSHR:(v[0-9]+.4s)]], [[UZP2]], #22
38 ; CHECK-NEXT: usra v0.4s, [[UZP2]], #31
49 ; CHECK-NEXT: ushr v0.16b, [[UZP2]], #5
60 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).8h]], [[UMULL]].8h, [[SMULL2]].8h
61 ; CHECK-NEXT: sub [[SUB:(v[0-9]+).8h]], v0.8h, [[UZP2]]
[all …]
H A Dneon-idiv.ll12 ; CHECK: uzp2 [[UZP2:(v[0-9]+).4s]], [[SMULL]].4s, [[SMULL2]].4s
13 ; CHECK: add [[ADD:(v[0-9]+.4s)]], [[UZP2]], v0.4s
H A Dsve-intrinsics-perm-select.ll1782 ; UZP2
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h184 UZP2, enumerator
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
H A DAArch64ISelLowering.cpp2129 MAKE_CASE(AArch64ISD::UZP2) in getTargetNodeName()
4580 return DAG.getNode(AArch64ISD::UZP2, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10205 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
10547 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
10560 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
11303 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR()
21835 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerFixedLengthVECTOR_SHUFFLEToSVE()
21845 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerFixedLengthVECTOR_SHUFFLEToSVE()
H A DAArch64SchedThunderX3T110.td1642 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64SchedA64FX.td1944 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td593 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
5309 // Prioritize ADDHN and SUBHN over UZP2.
5416 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;