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Searched refs:UREM (Results 1 – 25 of 63) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dudivrem-change-width.ll110 ; CHECK-NEXT: [[UREM:%.*]] = zext i8 [[TMP1]] to i32
111 ; CHECK-NEXT: ret i32 [[UREM]]
123 ; CHECK-NEXT: ret <2 x i32> [[UREM]]
135 ; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], [[ZB]]
151 ; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32
152 ; CHECK-NEXT: ret i32 [[UREM]]
210 ; CHECK-NEXT: ret i32 [[UREM]]
221 ; CHECK-NEXT: ret <2 x i32> [[UREM]]
231 ; CHECK-NEXT: [[UREM:%.*]] = urem i32 [[ZA]], 10
245 ; CHECK-NEXT: ret i32 [[UREM]]
[all …]
H A Dadd4.ll6 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
7 ; CHECK-NEXT: ret i64 [[UREM]]
20 ; CHECK-NEXT: [[UREM:%.*]] = urem <2 x i64> [[X:%.*]], <i64 19136, i64 19136>
21 ; CHECK-NEXT: ret <2 x i64> [[UREM]]
33 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
34 ; CHECK-NEXT: ret i64 [[UREM]]
H A Drem.ll341 ; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], [[X:%.*]]
342 ; CHECK-NEXT: ret i64 [[UREM]]
355 ; CHECK-NEXT: [[UREM:%.*]] = zext i32 [[TMP2]] to i64
356 ; CHECK-NEXT: ret i64 [[UREM]]
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dknown-power-of-two-urem.ll24 ; CHECK-NEXT: ret i64 [[UREM]]
62 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[UREM]], 10
65 ; CHECK-NEXT: ret i64 [[UREM]]
100 ; CHECK-NEXT: ret i64 [[UREM]]
124 ; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
160 ; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
195 ; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
230 ; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
265 ; CHECK-NEXT: [[ADD]] = add nsw i64 [[SUM]], [[UREM]]
300 ; CHECK-NEXT: [[ADD]] = add nsw i64 [[SUM]], [[UREM]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/RISCV/
H A Dicmp-zero.ll38 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], 16
67 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[M:%.*]]
99 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[M:%.*]]
136 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[M:%.*]]
137 ; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
161 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[NONZERO]]
192 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[VSCALE]]
224 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[MUL]]
258 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[MUL]]
291 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[SHL]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dzmmul.ll15 ; RUN: | not FileCheck -check-prefix=CHECK-UREM %s
17 ; RUN: | not FileCheck -check-prefix=CHECK-UREM %s
25 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
27 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
36 ; CHECK-UREM: remu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-legalize-urem.mir77 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $al = COPY [[UREM]](s8)
136 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
137 ; CHECK: $ax = COPY [[UREM]](s16)
191 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
192 ; CHECK: $eax = COPY [[UREM]](s32)
244 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
245 ; CHECK: $rax = COPY [[UREM]](s64)
H A Dx86-legalize-urem.mir76 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[LOAD]], [[LOAD1]]
77 ; CHECK: $al = COPY [[UREM]](s8)
138 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[LOAD]], [[LOAD1]]
139 ; CHECK: $ax = COPY [[UREM]](s16)
200 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[LOAD]], [[LOAD1]]
201 ; CHECK: $eax = COPY [[UREM]](s32)
H A Dx86_64-irtranslator.ll320 ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
321 ; CHECK: $al = COPY [[UREM]](s8)
335 ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
336 ; CHECK: $ax = COPY [[UREM]](s16)
348 ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
349 ; CHECK: $eax = COPY [[UREM]](s32)
361 ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
362 ; CHECK: $rax = COPY [[UREM]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcombine-udivrem-use-bug.mir15 ; CHECK-NEXT: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY]]
16 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UREM]], [[COPY]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Drem_and_div.mir93 ; MIPS32: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY1]], [[COPY]]
94 ; MIPS32: $v0 = COPY [[UREM]](s32)
H A Drem_and_div_vec.mir390 ; P5600: [[UREM:%[0-9]+]]:fprb(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
391 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
419 ; P5600: [[UREM:%[0-9]+]]:fprb(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
420 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
448 ; P5600: [[UREM:%[0-9]+]]:fprb(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
449 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
477 ; P5600: [[UREM:%[0-9]+]]:fprb(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
478 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Drem_and_div_vec.mir377 ; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
378 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
405 ; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
406 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
433 ; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
434 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
461 ; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
462 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div_vec_builtin.mir405 ; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
406 ; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
433 ; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
434 ; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
461 ; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
462 ; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
489 ; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
490 ; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div.mir411 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
413 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
442 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
444 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
470 ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
471 ; MIPS32: $v0 = COPY [[UREM]](s32)
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h111 case ISD::UREM:
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1344 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1348 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1352 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1356 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1361 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1365 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1369 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1373 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1928 case ISD::UREM: in maybeLoweredToCall()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h245 UREM, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Durem-opt-size.ll6 ; When the processor features hardware division, UDIV + UREM can be turned
H A Ddivmod-eabi.ll12 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1927 case ISD::UREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2049 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2050 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp323 case ISD::UREM: in LegalizeOp()
906 case ISD::UREM: in Expand()
1559 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h498 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp134 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
140 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()

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