Home
last modified time | relevance | path

Searched refs:UMLAL (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmisched-int-basic.mir61 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), …
123 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
H A Dbasic-arm-instructions.s3325 @ UMLAL
H A Dbasic-thumb2-instructions.s3700 @ UMLAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h265 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
H A DARMScheduleR52.td279 "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleSwift.td307 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMInstrInfo.td4401 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4435 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
6394 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6408 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMISelDAGToDAG.cpp3916 case ARMISD::UMLAL:{ in Select()
3930 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMISelLowering.cpp1808 MAKE_CASE(ARMISD::UMLAL) in getTargetNodeName()
12743 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
12850 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
12853 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
18591 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td529 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td5251 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
6513 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbasic-arm-instructions.txt2288 # UMLAL
H A Dthumb2.txt2428 # UMLAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8299 case ARM::UMLAL: in validateInstruction()