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Searched refs:UMAAL (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-armv7.txt364 # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
370 # A8.6.244 UMAAL
H A Dbasic-arm-instructions.txt2278 # UMAAL
H A Dthumb2.txt2416 # UMAAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h267 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply enumerator
H A DARMScheduleR52.td281 "UMAAL", "t2SMLAL", "t2UMLAL",
H A DARMScheduleSwift.td309 "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
H A DARMISelDAGToDAG.cpp3907 case ARMISD::UMAAL: { in Select()
3908 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
H A DARMScheduleA9.td2552 "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB",
H A DARMISelLowering.cpp1807 MAKE_CASE(ARMISD::UMAAL) in getTargetNodeName()
12872 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode), in AddCombineTo64bitUMAAL() local
12876 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1)); in AddCombineTo64bitUMAAL()
12877 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0)); in AddCombineTo64bitUMAAL()
12899 return DAG.getNode(ARMISD::UMAAL, SDLoc(N), in PerformUMLALCombine()
H A DARMInstrInfo.td4407 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-arm-instructions.s3315 @ UMAAL
H A Dbasic-thumb2-instructions.s3688 @ UMAAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8298 case ARM::UMAAL: in validateInstruction()