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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dudivrem-change-width.ll57 ; CHECK-NEXT: [[UDIV:%.*]] = zext i8 [[DIV]] to i32
58 ; CHECK-NEXT: ret i32 [[UDIV]]
70 ; CHECK-NEXT: ret <2 x i32> [[UDIV]]
82 ; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ZA]], [[ZB]]
98 ; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[DIV]] to i32
99 ; CHECK-NEXT: ret i32 [[UDIV]]
164 ; CHECK-NEXT: ret i32 [[UDIV]]
175 ; CHECK-NEXT: ret <2 x i32> [[UDIV]]
185 ; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ZA]], 10
199 ; CHECK-NEXT: ret i32 [[UDIV]]
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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dzmmul.ll11 ; RUN: | not FileCheck -check-prefix=CHECK-UDIV %s
13 ; RUN: | not FileCheck -check-prefix=CHECK-UDIV %s
25 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
27 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
30 ; CHECK-UDIV: divu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-legalize-udiv.mir77 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $al = COPY [[UDIV]](s8)
136 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
137 ; CHECK: $ax = COPY [[UDIV]](s16)
191 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
192 ; CHECK: $eax = COPY [[UDIV]](s32)
244 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
245 ; CHECK: $rax = COPY [[UDIV]](s64)
H A Dx86-legalize-udiv.mir72 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
73 ; CHECK: $al = COPY [[UDIV]](s8)
131 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
132 ; CHECK: $ax = COPY [[UDIV]](s16)
186 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
187 ; CHECK: $eax = COPY [[UDIV]](s32)
H A Dx86_64-irtranslator.ll264 ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
265 ; CHECK: $al = COPY [[UDIV]](s8)
279 ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
280 ; CHECK: $ax = COPY [[UDIV]](s16)
292 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
293 ; CHECK: $eax = COPY [[UDIV]](s32)
305 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
306 ; CHECK: $rax = COPY [[UDIV]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dcombine-udivrem-use-bug.mir16 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UREM]], [[COPY]]
17 ; CHECK-NEXT: $w0 = COPY [[UDIV]](s32)
H A Dlegalize-rem.mir10 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
11 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
104 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
105 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[UDIV]], [[AND1]]
181 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
185 …; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32)…
229 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[UV]], [[UV4]]
233 …; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UDIV]](s32), [[UDIV1]](s32)…
H A Dlegalize-divrem.mir10 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
11 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
13 ; CHECK: $x0 = COPY [[UDIV]](s64)
H A Dprelegalizer-combiner-divrem-insertpt-crash.mir30 ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[FREEZE]], [[C]]
32 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SHL]], [[UDIV]]
H A Dlegalize-div.mir21 ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
22 ; CHECK: $w0 = COPY [[UDIV]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/GlobalISel/
H A Dlegalize-udiv.mir27 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[AND]], [[AND1]]
28 ; CHECK-NEXT: $bd0 = COPY [[UDIV]](s8)
62 ; CHECK-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
63 ; CHECK-NEXT: $d0 = COPY [[UDIV]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Drem_and_div.mir70 ; MIPS32: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY1]], [[COPY]]
71 ; MIPS32: $v0 = COPY [[UDIV]](s32)
H A Drem_and_div_vec.mir274 ; P5600: [[UDIV:%[0-9]+]]:fprb(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
275 ; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
303 ; P5600: [[UDIV:%[0-9]+]]:fprb(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
304 ; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
332 ; P5600: [[UDIV:%[0-9]+]]:fprb(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
333 ; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
361 ; P5600: [[UDIV:%[0-9]+]]:fprb(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
362 ; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Drem_and_div_vec.mir265 ; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
266 ; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
293 ; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
294 ; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
321 ; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
322 ; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
349 ; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
350 ; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div_vec_builtin.mir293 ; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
294 ; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
321 ; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
322 ; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
349 ; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
350 ; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
377 ; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
378 ; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div.mir288 ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
290 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
319 ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
321 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
347 ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY1]], [[COPY]]
348 ; MIPS32: $v0 = COPY [[UDIV]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Durem-opt-size.ll6 ; When the processor features hardware division, UDIV + UREM can be turned
7 ; into UDIV + MLS. This prevents the library function __aeabi_uidivmod to be
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h110 case ISD::UDIV:
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Dumodsi3.S70 # error THUMB mode requires CLZ or UDIV
H A Dudivmodsi4.S73 # error THUMB mode requires CLZ or UDIV
H A Dudivsi3.S96 # error THUMB mode requires CLZ or UDIV
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1342 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1346 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1350 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
1354 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
1359 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1363 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1367 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1371 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1926 case ISD::UDIV: in maybeLoweredToCall()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def99 ADD_BINARY_VVP_OP_COMPACT(UDIV)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h243 UDIV, enumerator
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
284 if (ISD == ISD::UDIV) in getArithmeticInstrCost()
381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence in getArithmeticInstrCost()
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