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Searched refs:TargetSchedModel (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp38 bool TargetSchedModel::hasInstrSchedModel() const { in hasInstrSchedModel()
42 bool TargetSchedModel::hasInstrItineraries() const { in hasInstrItineraries()
62 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) { in init()
84 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI, in mustBeginGroup()
95 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI, in mustEndGroup()
106 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, in getNumMicroOps()
131 const MCSchedClassDesc *TargetSchedModel::
183 unsigned TargetSchedModel::computeOperandLatency( in computeOperandLatency()
272 TargetSchedModel::computeInstrLatency(const MachineInstr *MI, in computeInstrLatency()
288 unsigned TargetSchedModel::
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H A DMachineTraceMetrics.cpp126 for (TargetSchedModel::ProcResIter in getResources()
894 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
955 const TargetSchedModel &SchedModel, in pushDepHeight()
1240 for (TargetSchedModel::ProcResIter in getResourceLength()
H A DVLIWMachineScheduler.cpp66 const TargetSchedModel *SM) in VLIWResourceModel()
306 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
H A DMachineScheduler.cpp2019 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init()
2028 for (TargetSchedModel::ProcResIter in init()
2039 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { in init()
2442 for (TargetSchedModel::ProcResIter in bumpNode()
2455 for (TargetSchedModel::ProcResIter in bumpNode()
2623 const TargetSchedModel *SchedModel) { in initResourceDelta()
2628 for (TargetSchedModel::ProcResIter in initResourceDelta()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DVLIWMachineScheduler.h40 const TargetSchedModel *SchedModel;
50 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM);
128 const TargetSchedModel *SchedModel = nullptr;
155 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { in init()
208 const TargetSchedModel *SchedModel = nullptr;
242 const TargetSchedModel *SchedModel) const;
H A DTargetSchedule.h30 class TargetSchedModel {
49 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {} in TargetSchedModel() function
H A DTargetSubtargetInfo.h51 class TargetSchedModel; variable
143 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
H A DMachineScheduler.h605 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
621 const TargetSchedModel *SchedModel = nullptr;
702 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
906 const TargetSchedModel *SchedModel);
911 const TargetSchedModel *SchedModel = nullptr;
H A DScheduleDAGInstrs.h125 TargetSchedModel SchedModel;
262 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel()
H A DMachineTraceMetrics.h93 TargetSchedModel SchedModel;
H A DTargetInstrInfo.h60 class TargetSchedModel; variable
1641 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
1651 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h48 const TargetSchedModel *SchedModel;
111 const TargetSchedModel *SM) in SystemZHazardRecognizer()
H A DSystemZHazardRecognizer.cpp175 for (TargetSchedModel::ProcResIter in dumpSU()
296 for (TargetSchedModel::ProcResIter in EmitInstruction()
400 for (TargetSchedModel::ProcResIter in resourcesCost()
H A DSystemZMachineScheduler.h38 TargetSchedModel SchedModel;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h35 const TargetSchedModel *SchedModel) const override;
H A DHexagonMachineScheduler.cpp41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h49 TargetSchedModel TSchedModel;
H A DAMDGPUIGroupLP.cpp261 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel(); in apply()
294 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel(); in apply()
H A DAMDGPUInsertDelayAlu.cpp33 TargetSchedModel SchedModel;
H A DSIInstrInfo.h48 TargetSchedModel SchedModel;
1178 const TargetSchedModel &getSchedModel() const { return SchedModel; } in getSchedModel()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp34 TargetSchedModel SchedModel;
H A DAArch64Schedule.td10 // const MachineInstr *MI and const TargetSchedModel *SchedModel
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp93 TargetSchedModel TSM;
H A DX86InstrInfo.h497 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h461 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
466 bool hasLowDefLatency(const TargetSchedModel &SchedModel,

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