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Searched refs:TailShXAdd (Results 1 – 1 of 1) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp53 bool matchShiftedOffset(MachineInstr &TailShXAdd, Register GSReg,
207 bool RISCVMergeBaseOffsetOpt::matchShiftedOffset(MachineInstr &TailShXAdd, in matchShiftedOffset() argument
210 assert((TailShXAdd.getOpcode() == RISCV::SH1ADD || in matchShiftedOffset()
211 TailShXAdd.getOpcode() == RISCV::SH2ADD || in matchShiftedOffset()
212 TailShXAdd.getOpcode() == RISCV::SH3ADD) && in matchShiftedOffset()
216 Register Rs1 = TailShXAdd.getOperand(1).getReg(); in matchShiftedOffset()
218 if (GAReg != TailShXAdd.getOperand(2).getReg()) in matchShiftedOffset()
237 switch (TailShXAdd.getOpcode()) { in matchShiftedOffset()