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Searched refs:TSTri (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dtst-peephole.mir36 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
50 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
H A Dmovc-peephole.mir27 ; CHECK-NEXT: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
38 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp117 unsigned TSTri; member
328 STORE_OPCODE(TSTri, TSTri); in OpcodeCache()
777 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri)) in selectSelect()
1125 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri)) in select()
H A DARMMCInstLower.cpp135 case ARM::TSTri: in LowerARMMachineInstrToMCInst()
H A DARMFastISel.cpp1262 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectBranch()
1300 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectBranch()
1636 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; in SelectSelect()
H A DARMBaseInstrInfo.cpp2818 case ARM::TSTri: in analyzeCompare()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-instruction-select.mir1183 ; CHECK: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
1218 ; CHECK: TSTri [[COPY2]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
1249 ; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
1296 ; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
/llvm-project-15.0.7/llvm/docs/
H A DMIRLangRef.rst379 similar instruction names like ``TSTri`` and ``tSTRi`` represent different