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Searched refs:TSR (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrHTM.td64 def TSR : XForm_htm2 <31, 750,
128 (TSR (HTM_get_imm imm:$L))>;
161 (TSR 1)>;
164 (TSR 0)>;
174 def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
175 def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;
H A DP10InstrResources.td1187 TSR
H A DP9InstrResources.td200 TSR,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp204 unsigned TSR, unsigned FR, unsigned FSR);
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux() argument
805 .addReg(TR, 0, TSR) in buildMux()
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local
824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
833 TR = SR, TSR = SSR; in updatePhiNodes()
844 FP.PredR, TR, TSR, FR, FSR); in updatePhiNodes()
847 MuxSR = TSR; in updatePhiNodes()