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Searched refs:TSFlags (Results 1 – 25 of 125) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h140 return TSFlags & HasDummyMaskOpMask; in hasDummyMaskOp()
148 return TSFlags & HasMergeOpMask; in hasMergeOp()
152 return TSFlags & HasSEWOpMask; in hasSEWOp()
156 return TSFlags & HasVLOpMask; in hasVLOp()
160 return TSFlags & HasVecPolicyOpMask; in hasVecPolicyOp()
172 const uint64_t TSFlags = Desc.TSFlags; in getVLOpNum() local
175 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags)); in getVLOpNum()
177 if (hasVecPolicyOp(TSFlags)) in getVLOpNum()
183 const uint64_t TSFlags = Desc.TSFlags; in getSEWOpNum() local
184 assert(hasSEWOp(TSFlags)); in getSEWOpNum()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h356 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
364 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
380 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
490 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
494 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
522 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
527 auto Flags = get(Opcode).TSFlags; in isSegmentSpecificFLAT()
565 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
599 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
631 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
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H A DSIInstrFormats.td154 let TSFlags{0} = SALU;
155 let TSFlags{1} = VALU;
157 let TSFlags{2} = SOP1;
158 let TSFlags{3} = SOP2;
159 let TSFlags{4} = SOPC;
160 let TSFlags{5} = SOPK;
161 let TSFlags{6} = SOPP;
163 let TSFlags{7} = VOP1;
164 let TSFlags{8} = VOP2;
165 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
66 let TSFlags{15} = LDS_1A;
67 let TSFlags{16} = LDS_1A1D;
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H A DAMDGPUInsertDelayAlu.cpp48 if (MI.getDesc().TSFlags & VA_VDST_0) in instructionWaitsForVALU()
63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
64 if (TSFlags & SIInstrFlags::TRANS) in getDelayType()
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
68 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
348 DelayType Type = getDelayType(MI.getDesc().TSFlags); in runOnMachineBasicBlock()
H A DSIPostRABundler.cpp110 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
116 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
120 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DR600Defines.h59 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
60 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
87 let TSFlags{10} = isPredicated;
126 let TSFlags{36} = cofMax1;
128 let TSFlags{37} = cofRelax1;
130 let TSFlags{38} = cofRelax2;
164 let TSFlags{62} = CVINew;
167 let TSFlags{63} = isCVI;
289 let TSFlags{6-0} = Type.Value;
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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.cpp156 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
167 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
181 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
183 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
212 if (Desc.TSFlags & X86II::EVEX_B) in printVecCompareInstr()
310 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
321 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
324 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
331 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
333 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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H A DX86MCCodeEmitter.cpp599 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags; in emitPrefixImpl() local
665 uint64_t TSFlags = Desc.TSFlags; in emitVEXOpcodePrefix() local
1125 uint64_t TSFlags = Desc.TSFlags; in emitREXPrefix() local
1127 if (TSFlags & X86II::REX_W) in emitREXPrefix()
1251 uint64_t TSFlags = Desc.TSFlags; in emitOpcodePrefix() local
1311 uint64_t TSFlags = Desc.TSFlags; in emitPrefix() local
1327 uint64_t TSFlags = Desc.TSFlags; in encodeInstruction() local
1392 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1399 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1407 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
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H A DX86ATTInstPrinter.cpp177 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
183 } else if (Desc.TSFlags & X86II::VEX_W) { in printVecCompareInstr()
191 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
193 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
221 if (Desc.TSFlags & X86II::EVEX_B) in printVecCompareInstr()
333 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
336 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
343 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
345 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
351 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86BaseInfo.h974 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
979 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
986 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
989 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
990 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
996 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
1013 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
1032 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
1099 switch (TSFlags & X86II::FormMask) { in getMemoryOperandNo()
1226 return (TSFlags & X86II::EVEX_K) != 0; in isKMasked()
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H A DX86InstPrinterCommon.cpp356 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
359 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
362 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
371 if ((Flags & X86::IP_USE_VEX) || (TSFlags & X86II::ExplicitVEXPrefix)) in printInstFlags()
386 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in printInstFlags()
392 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { in printInstFlags()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DRegisterInfoEmitter-tsflags.td3 // Configure and test TSFlags for a target.
18 // Associate the defined bitfields to unique bit positions in TSFlags.
19 let TSFlags{0} = A;
20 let TSFlags{2-1} = B;
23 // Default value for TSFlags.
42 // CHECK: 0x07, /* TSFlags */
44 // CHECK: 0x06, /* TSFlags */
46 // CHECK: 0x00, /* TSFlags */
48 // CHECK: 0x01, /* TSFlags */
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp247 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
248 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
252 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
268 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
269 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
280 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()
282 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
284 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
301 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
302 MCID.TSFlags & SIInstrFlags::MTBUF || in isVMEM()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp141 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
144 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
148 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
149 (TSFlags & X86II::OpMapMask) == X86II::T8) || in getFMA3Group()
150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
151 ((TSFlags & X86II::OpMapMask) == X86II::T8 || in getFMA3Group()
152 (TSFlags & X86II::OpMapMask) == X86II::T_MAP6)); in getFMA3Group()
153 bool IsFMA3Prefix = (TSFlags & X86II::OpPrefixMask) == X86II::PD; in getFMA3Group()
160 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
162 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86EvexToVex.cpp226 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEvexToVexImpl()
232 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) in CompressEvexToVexImpl()
237 if (Desc.TSFlags & X86II::EVEX_L2) in CompressEvexToVexImpl()
254 (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable) in CompressEvexToVexImpl()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
515 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp368 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
369 if (RISCVII::hasSEWOp(TSFlags)) { in getDemanded()
371 if (RISCVII::hasVLOp(TSFlags)) in getDemanded()
829 if (RISCVII::hasVLOp(TSFlags)) { in computeInfoForInstr()
993 uint64_t TSFlags = MI.getDesc().TSFlags; in transferBefore() local
994 if (!RISCVII::hasSEWOp(TSFlags)) in transferBefore()
1004 if (!RISCVII::hasVLOp(TSFlags)) in transferBefore()
1203 uint64_t TSFlags = MI.getDesc().TSFlags; in emitVSETVLIs() local
1204 if (RISCVII::hasSEWOp(TSFlags)) { in emitVSETVLIs()
1334 const uint64_t TSFlags = MI.getDesc().TSFlags; in doPRE() local
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H A DRISCVMCInstLower.cpp151 uint64_t TSFlags = MI->getDesc().TSFlags; in lowerRISCVVMachineInstrToMCInst() local
155 if (RISCVII::hasVecPolicyOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
157 if (RISCVII::hasVLOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
159 if (RISCVII::hasSEWOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
170 if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) { in lowerRISCVVMachineInstrToMCInst()
207 if (RISCVII::hasDummyMaskOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
H A DRISCVInstrFormats.td171 let TSFlags{4-0} = format.Value;
175 let TSFlags{7-5} = RVVConstraint.Value;
178 let TSFlags{10-8} = VLMul;
181 let TSFlags{11} = HasDummyMask;
184 let TSFlags{12} = ForceTailAgnostic;
187 let TSFlags{13} = HasMergeOp;
190 let TSFlags{14} = HasSEWOp;
193 let TSFlags{15} = HasVLOp;
196 let TSFlags{16} = HasVecPolicyOp;
199 let TSFlags{17} = IsRVVWideningReduction;
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp32 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
53 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
63 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
113 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
115 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp134 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
135 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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