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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-args-06.ll11 ; CHECK: larl [[TMP:%r[0-5]]], .LCPI
12 ; CHECK: vl %v24, 0([[TMP]])
13 ; CHECK: larl [[TMP:%r[0-5]]], .LCPI
14 ; CHECK: vl %v26, 0([[TMP]])
15 ; CHECK: larl [[TMP:%r[0-5]]], .LCPI
16 ; CHECK: vl %v28, 0([[TMP]])
18 ; CHECK: vl %v30, 0([[TMP]])
20 ; CHECK: vl %v25, 0([[TMP]])
22 ; CHECK: vl %v27, 0([[TMP]])
24 ; CHECK: vl %v29, 0([[TMP]])
[all …]
H A Dargs-07.ll33 ; CHECK: larl [[TMP:%r[0-5]]], .LCPI
34 ; CHECK: ld %f0, 0([[TMP]])
35 ; CHECK: larl [[TMP:%r[0-5]]], .LCPI
36 ; CHECK: ld %f2, 0([[TMP]])
38 ; CHECK: ld %f4, 0([[TMP]])
40 ; CHECK: ld %f6, 0([[TMP]])
58 ; CHECK: stg [[TMP]], 32(%r2)
60 ; CHECK: stg [[TMP]], 24(%r2)
62 ; CHECK: stg [[TMP]], 16(%r2)
64 ; CHECK: stg [[TMP]], 8(%r2)
[all …]
H A Dcmpxchg-01.ll67 ; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
68 ; CHECK-MAIN: risbg %r5, [[TMP]], 32, 55, 0
69 ; CHECK-MAIN: llcr [[TMP2:%r[0-9]+]], [[TMP]]
104 ; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r2)
105 ; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
106 ; CHECK-MAIN: llcr [[TMP]], [[TMP]]
107 ; CHECK-MAIN: cr [[TMP]], %r3
143 ; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r2)
144 ; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
145 ; CHECK-MAIN: llcr [[TMP]], [[TMP]]
[all …]
/llvm-project-15.0.7/llvm/utils/TableGen/
H A Dtdtags118 >$TMP:D
151 >$TMP:E
152 >$TMP:J
165 sort -u <$TMP:E >$TMP:X
166 sort -u <$TMP:J >$TMP:I
168 comm -23 $TMP:X $TMP:I >$TMP:T
192 done <$TMP:I
203 done <$TMP:D
222 done <$TMP:T
241 sort -m -u $TMP:A:* >$TMP:M
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Ddfmul.S41 #define TMP r28 macro
226 TMP = USR define
246 USR = TMP
260 TMP = USR define
266 TMP = or(TMP,#0x28) // inexact + overflow define
270 USR = TMP
335 TMP = add(TMP,#-EXPBITS) define
347 TMP = USR define
351 TMP = or(TMP,#0x30) // Inexact + Underflow define
356 USR = TMP
[all …]
H A Ddffma.S56 #define TMP r28 macro
225 TMP = #63 define
248 TMP = #-2 define
266 TMP = #62 define
324 TMP = USR define
328 TMP = extractu(TMP,#2,#SR_ROUND_OFF) define
407 TMP = #63 define
469 TMP = USR define
476 TMP = or(TMP,#0x28) define
652 TMP = extractu(TMP,#2,#SR_ROUND_OFF) define
[all …]
H A Ddfdiv.S250 TMP = USR define
275 USR = TMP
312 TMP = or(TMP,#0x30) define
315 USR = TMP
327 TMP = USR define
334 TMP = or(TMP,#0x28) define
337 USR = TMP
413 TMP = #1 define
448 TMP = USR define
453 TMP = or(TMP,#0x04) // DBZ define
[all …]
H A Ddfaddsub.S42 #define TMP r28 macro
164 TMP = USR define
169 TMP = extractu(TMP,#2,#22) define
173 p0 = cmp.eq(TMP,#2)
213 TMP = sub(#1,EXPB) define
220 B = lsr(B,TMP)
231 TMP = USR define
236 TMP = or(TMP,#0x28) // inexact + overflow define
240 USR = TMP
371 TMP = USR define
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dunaligned_load_store_vfp.ll5 ; CHECK: ldr [[TMP:r[0-9]+]], [r0]
6 ; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
16 ; CHECK: ldr [[TMP:r[0-9]+]], [r0]
17 ; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
27 ; CHECK: ldr [[TMP:r[0-9]+]], [r0]
28 ; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
38 ; CHECK: ldr [[TMP:r[0-9]+]], [r0]
39 ; CHECK: vmov [[RES_INT:s[0-9]+]], [[TMP]]
49 ; CHECK: vmov [[TMP:r[0-9]+]], s0
50 ; CHECK: str [[TMP]], [r0]
[all …]
H A Ddag-combine-ldst.ll9 ; CHECK: mov [[TMP:r[0-9]+]], #0
10 ; CHECK-NEXT: str [[TMP]], [sp, #4]
11 ; CHECK_O0: str [[TMP]], [sp]
12 ; CHECK_O0: ldr [[TMP:r[0-9]+]], [sp]
13 ; CHECK_O0-NEXT: add [[TMP]], [[TMP]], #2
14 ; CHECK_O1-NOT: ldr [[TMP:r[0-9]+]], [sp]
15 ; CHECK_O1-NOT: add [[TMP]], [[TMP]], #2
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dknown-never-nan.ll15 ; CHECK-NEXT: ret i1 [[TMP]]
28 ; CHECK-NEXT: ret i1 [[TMP]]
41 ; CHECK-NEXT: ret i1 [[TMP]]
55 ; CHECK-NEXT: ret i1 [[TMP]]
69 ; CHECK-NEXT: ret i1 [[TMP]]
82 ; CHECK-NEXT: ret i1 [[TMP]]
96 ; CHECK-NEXT: ret i1 [[TMP]]
111 ; CHECK-NEXT: ret i1 [[TMP]]
147 ; CHECK-NEXT: ret i1 [[TMP]]
158 ; CHECK-NEXT: ret i1 [[TMP]]
[all …]
H A Dscalable-cast-of-alloc.ll7 ; CHECK-NEXT: [[TMP:%.*]] = alloca [16 x i32], align 16
8 ; CHECK-NEXT: [[CAST:%.*]] = bitcast [16 x i32]* [[TMP]] to <vscale x 4 x i32>*
26 ; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 4 x i32>, align 64
27 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <vscale x 4 x i32>* [[TMP]] to <16 x i32>*
45 ; CHECK-NEXT: [[TMP:%.*]] = alloca <16 x i32>, align 16
46 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i32>* [[TMP]] to <vscale x 4 x i32>*
64 ; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 16 x i32>, align 64
65 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <vscale x 16 x i32>* [[TMP]] to <16 x i32>*
83 ; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 32 x i32>, align 64
102 ; CHECK-NEXT: [[TMP:%.*]] = alloca <vscale x 16 x i32>, align 64
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A DmemInstructions.3.2.ll228 ; CHECK-NEXT: %res1 = extractvalue { i32, i1 } [[TMP]], 0
232 ; CHECK-NEXT: %res2 = extractvalue { i32, i1 } [[TMP]], 0
236 ; CHECK-NEXT: %res3 = extractvalue { i32, i1 } [[TMP]], 0
240 ; CHECK-NEXT: %res4 = extractvalue { i32, i1 } [[TMP]], 0
245 ; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
249 ; CHECK-NEXT: %res6 = extractvalue { i32, i1 } [[TMP]], 0
253 ; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
257 ; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
262 ; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
266 ; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-fast-isel-rem.ll15 ; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
16 ; CHECK: msub w0, [[TMP]], w1, w0
23 ; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
24 ; CHECK: msub x0, [[TMP]], x1, x0
31 ; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
32 ; CHECK: msub w0, [[TMP]], w1, w0
39 ; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
40 ; CHECK: msub x0, [[TMP]], x1, x0
H A Dswift-return.ll8 ; CHECK: sxth [[TMP:w.*]], w0
12 ; CHECK-O0: sxth [[TMP:w.*]], w0
31 ; CHECK: add [[TMP]], [[TMP]], x2
32 ; CHECK: add [[TMP]], [[TMP]], x3
33 ; CHECK: add x0, [[TMP]], x4
37 ; CHECK-O0: add [[TMP]], [[TMP]], x2
38 ; CHECK-O0: add [[TMP]], [[TMP]], x3
78 ; CHECK: add [[TMP]], [[TMP]], w2
83 ; CHECK-O0: add [[TMP]], [[TMP]], w2
162 ; CHECK-DAG: add [[TMP]], [[TMP]], w2
[all …]
H A Darm64-neon-mul-div-cte.ll17 ; CHECK: mov [[TMP:(w[0-9]+)]], #40815
18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
31 ; CHECK: mov [[TMP:(w[0-9]+)]], #7527
32 ; CHECK-NEXT: movk [[TMP]], #28805, lsl #16
33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
56 ; CHECK: mov [[TMP:(w[0-9]+)]], #16593
57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]]
70 ; CHECK: mov [[TMP:(w[0-9]+)]], #16747
71 ; CHECK-NEXT: movk [[TMP]], #31439, lsl #16
72 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]]
H A Darm64_32-atomics.ll161 ; CHECK: stxrb [[TMP:w[0-9]+]], w1, [x0]
162 ; CHECK: mov w0, [[TMP]]
172 ; CHECK: mov w0, [[TMP]]
181 ; CHECK: stxr [[TMP:w[0-9]+]], w1, [x0]
182 ; CHECK: mov w0, [[TMP]]
191 ; CHECK: stxr [[TMP:w[0-9]+]], x1, [x0]
192 ; CHECK: mov w0, [[TMP]]
206 ; CHECK: mov w0, [[TMP]]
216 ; CHECK: mov w0, [[TMP]]
226 ; CHECK: mov w0, [[TMP]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/
H A Dmin-legal-vector-width.ll44 ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
57 ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
71 ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
84 ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
138 ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
151 ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
165 ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
178 ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
232 ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
245 ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
[all …]
H A Dattributes.ll39 ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
41 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
52 ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
54 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
65 ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
67 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8*
78 ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
128 ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
141 ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
155 ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlo16-lo16-physreg-copy-agpr.mir4 # GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a0
6 # GCN-NEXT: v_accvgpr_write_b32 a1, [[TMP]]
29 # GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a1
31 # GCN-NEXT: v_accvgpr_write_b32 a2, [[TMP]]
42 # GCN: v_mov_b32_e32 [[TMP:v[0-9]+]], s0
44 # GCN-NEXT: v_accvgpr_write_b32 a1, [[TMP]]
H A Dfmuladd.f32.ll101 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
132 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
165 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
166 ; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
201 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
231 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
263 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
296 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
328 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
575 ; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dknown-never-nan.ll62 ; CHECK-NEXT: ret i1 [[TMP]]
188 ; CHECK-NEXT: ret i1 [[TMP]]
201 ; CHECK-NEXT: ret i1 [[TMP]]
215 ; CHECK-NEXT: ret i1 [[TMP]]
229 ; CHECK-NEXT: ret i1 [[TMP]]
242 ; CHECK-NEXT: ret i1 [[TMP]]
256 ; CHECK-NEXT: ret i1 [[TMP]]
271 ; CHECK-NEXT: ret i1 [[TMP]]
296 ; CHECK-NEXT: ret i1 [[TMP]]
337 ; CHECK-NEXT: ret i1 [[TMP]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/X86/
H A Dmin-legal-vector-width.ll26 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
28 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8*
65 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
104 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
143 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
170 ; CHECK-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]]
183 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
209 ; CHECK-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]]
222 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
260 ; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
[all …]
/llvm-project-15.0.7/clang/test/Driver/
H A Dspirv-toolchain.cl52 // RUN: %clang -### --target=spirv64 -x cl -c %s --save-temps 2>&1 | FileCheck --check-prefix=TMP %s
54 // TMP: "-cc1" "-triple" "spirv64"
55 // TMP-SAME: "-E"
56 // TMP-SAME: "-o" [[I:".*i"]]
57 // TMP: "-cc1" "-triple" "spirv64"
58 // TMP-SAME: "-o" [[BC:".*bc"]]
59 // TMP-SAME: [[I]]
60 // TMP: {{llvm-spirv.*"}} [[BC]] "--spirv-tools-dis" "-o" [[S:".*s"]]
61 // TMP: {{llvm-spirv.*"}} [[S]] "-to-binary" "-o" {{".*o"}}
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dcl20-device-side-enqueue.cl135 // B32-SAME: i32* %[[TMP]])
136 // B64-SAME: i64* %[[TMP]])
160 // B32-SAME: i32* %[[TMP]])
161 // B64-SAME: i64* %[[TMP]])
187 // B32-SAME: i32* %[[TMP]])
188 // B64-SAME: i64* %[[TMP]])
214 // B32-SAME: i32* %[[TMP]])
215 // B64-SAME: i64* %[[TMP]])
239 // B32-SAME: i32* %[[TMP]])
240 // B64-SAME: i64* %[[TMP]])
[all …]

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