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/llvm-project-15.0.7/clang-tools-extra/clangd/support/
H A DTrace.cpp80 uint64_t TID = llvm::get_threadid(), double Timestamp = 0) { in jsonEvent() argument
82 Contents["tid"] = int64_t(TID); in jsonEvent()
92 TID(llvm::get_threadid()), Tracer(Tracer) { in JSONSpan()
102 if (Parent && *Parent && (*Parent)->TID != TID) { in JSONSpan()
115 (*Parent)->TID, (*Parent)->StartTime); in JSONSpan()
122 TID); in JSONSpan()
132 TID, StartTime); in ~JSONSpan()
149 uint64_t TID; member in clang::clangd::trace::__anonf4523cc60111::JSONTracer::JSONSpan
169 uint64_t TID = llvm::get_threadid(); in captureThreadMetadata() local
171 if (ThreadsWithMD.insert(TID).second) { in captureThreadMetadata()
[all …]
/llvm-project-15.0.7/llvm/lib/XRay/
H A DFDRTraceExpander.cpp45 CurrentRecord.TId = TID; in visit()
60 CurrentRecord.TId = TID; in visit()
75 CurrentRecord.TId = TID; in visit()
98 TID = R.tid(); in visit()
118 CurrentRecord.TId = TID; in visit()
H A DProfile.cpp389 const auto &TID = ThreadPaths.first; in profileFromTrace() local
392 TID, in profileFromTrace()
H A DRecordInitializer.cpp356 R.TID = E.getSigned(&OffsetPtr, sizeof(int32_t)); in visit()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcallee-special-input-vgprs-packed.ll124 ; PACKED-TID: v_mov_b32_e32 v31, v0
141 ; PACKED-TID: v_mov_b32_e32 v31, v0
156 ; PACKED-TID: v_mov_b32_e32 v31, v0
171 ; PACKED-TID: v_mov_b32_e32 v31, v0
185 ; PACKED-TID: v_mov_b32_e32 v31, v0
202 ; PACKED-TID: v_mov_b32_e32 v31, v0
297 ; PACKED-TID: v_mov_b32_e32 v31, v0
646 ; PACKED-TID-NOT: v0
647 ; PACKED-TID-NOT: v1
648 ; PACKED-TID-NOT: v2
[all …]
H A Dllvm.amdgcn.workitem.id.ll7 …nknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s
8 …1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s
24 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 0
40 ; PACKED-TID: v_bfe_u32 [[ID:v[0-9]+]], v0, 10, 10
41 ; PACKED-TID: {{buffer|flat|global}}_store_{{dword|b32}} {{.*}}[[ID]]
42 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 1
58 ; PACKED-TID: v_bfe_u32 [[ID:v[0-9]+]], v0, 20, 10
59 ; PACKED-TID: {{buffer|flat|global}}_store_{{dword|b32}} {{.*}}[[ID]]
60 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 2
H A Dcgp-addressing-modes-gfx1030.ll11 ; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #[[ATTR3:[0-9]+]]
12 ; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
H A Dcgp-addressing-modes-gfx908.ll10 ; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #[[ATTR3:[0-9]+]]
11 ; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
H A Dunstructured-cfg-def-use-issue.ll131 ; SI-OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
132 ; SI-OPT-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* null, i32 [[TID]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.workitem.id.ll7 …nknown-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s
8 …1100 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=ALL,PACKED-TID %s
24 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 0
40 ; PACKED-TID: v_bfe_u32 [[ID:v[0-9]+]], v0, 10, 10
41 ; PACKED-TID: {{buffer|flat|global}}_store_{{dword|b32}} {{.*}}[[ID]]
42 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 1
58 ; PACKED-TID: v_bfe_u32 [[ID:v[0-9]+]], v0, 20, 10
59 ; PACKED-TID: {{buffer|flat|global}}_store_{{dword|b32}} {{.*}}[[ID]]
60 ; PACKED-TID: .amdhsa_system_vgpr_workitem_id 2
/llvm-project-15.0.7/llvm/test/Transforms/OpenMP/
H A Dfold_generic_main_thread.ll58 ; CHECK-NEXT: [[TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id()
68 ; CHECK-DISABLED-NEXT: [[TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id()
69 …K-DISABLED-NEXT: [[ISMAIN:%.*]] = call signext i8 @__kmpc_is_generic_main_thread_id(i32 [[TID]])
96 ; CHECK-NEXT: [[TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id()
97 ; CHECK-NEXT: [[ISMAIN:%.*]] = call signext i8 @__kmpc_is_generic_main_thread_id(i32 [[TID]])
108 ; CHECK-DISABLED-NEXT: [[TID:%.*]] = call i32 @__kmpc_get_hardware_thread_id()
109 …K-DISABLED-NEXT: [[ISMAIN:%.*]] = call signext i8 @__kmpc_is_generic_main_thread_id(i32 [[TID]])
H A Dparallel_region_merging.ll813 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
932 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1005 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1083 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1160 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1241 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1319 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1385 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1471 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
1536 ; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
[all …]
/llvm-project-15.0.7/openmp/docs/remarks/
H A DOMP131.rst24 int TID;
30 TID = omp_get_thread_num();
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/AMDGPU/
H A Daddressing-modes.ll9 ; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
10 ; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[TID]], 0
/llvm-project-15.0.7/flang/test/Semantics/OpenMP/
H A Domp-do18.f9032 write (*,100) TID, I, C(I)
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp435 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in SUSchedulingCost() local
436 if (TID.isCall()) in SUSchedulingCost()
537 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in initNumRegDefsLeft() local
543 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs()); in initNumRegDefsLeft()
/llvm-project-15.0.7/llvm/include/llvm/XRay/
H A DFDRTraceExpander.h27 int32_t TID = 0; variable
H A DFDRRecords.h337 int32_t TID = 0; variable
348 TID(T) {} in NewBufferRecord()
350 int32_t tid() const { return TID; } in tid()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp933 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca() local
934 TID = Builder.CreateAdd(TID, TIdZ); in handleAlloca()
938 TID in handleAlloca()
/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/AMDGPU/
H A Dbackedge-id-bug.ll22 ; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
23 …HECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]
H A Dloop-subregion-misordered.ll26 ; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
27 …HECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstr.h272 MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
1716 void setDesc(const MCInstrDesc &TID) { MCID = &TID; }
/llvm-project-15.0.7/mlir/test/Dialect/GPU/
H A Doutlining.mlir47 // CHECK-NEXT: %[[TID:.*]] = gpu.thread_id x
60 // CHECK-NEXT: = memref.load %[[KERNEL_ARG1]][%[[TID]]] : memref<?xf32, 1>
/llvm-project-15.0.7/llvm/lib/IR/
H A DType.cpp661 VectorType::VectorType(Type *ElType, unsigned EQ, Type::TypeID TID) in VectorType() argument
662 : Type(ElType->getContext(), TID), ContainedType(ElType), in VectorType()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcast_phi.ll12 ; CHECK-NEXT: [[CONV_I12:%.*]] = zext i32 [[TID:%.*]] to i64
17 ; CHECK-NEXT: [[CMP7:%.*]] = icmp eq i32 [[TID]], 0

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