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Searched refs:TEMP (Results 1 – 25 of 55) sorted by relevance

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/llvm-project-15.0.7/polly/lib/External/isl/imath/
H A Dimath.c1195 REQUIRE(mp_int_sub(TEMP(0), TEMP(1), TEMP(2))); in mp_int_gcd()
1260 REQUIRE(mp_int_add(TEMP(0), TEMP(7), TEMP(0))); in mp_int_egcd()
1261 REQUIRE(mp_int_sub(TEMP(1), TEMP(6), TEMP(1))); in mp_int_egcd()
1281 REQUIRE(mp_int_sub(TEMP(4), TEMP(5), TEMP(4))); in mp_int_egcd()
1282 REQUIRE(mp_int_sub(TEMP(0), TEMP(2), TEMP(0))); in mp_int_egcd()
1283 REQUIRE(mp_int_sub(TEMP(1), TEMP(3), TEMP(1))); in mp_int_egcd()
1285 REQUIRE(mp_int_sub(TEMP(5), TEMP(4), TEMP(5))); in mp_int_egcd()
1286 REQUIRE(mp_int_sub(TEMP(2), TEMP(0), TEMP(2))); in mp_int_egcd()
1287 REQUIRE(mp_int_sub(TEMP(3), TEMP(1), TEMP(3))); in mp_int_egcd()
1372 REQUIRE(mp_int_sub(TEMP(2), TEMP(0), TEMP(2))); in mp_int_root()
[all …]
H A Dimrat.c421 cmp = mp_int_compare_unsigned(TEMP(0), TEMP(1)); in mp_rat_compare_unsigned()
506 mp_int_abs(TEMP(0), TEMP(0)); in mp_rat_to_decimal()
507 if ((res = mp_int_div(TEMP(0), MP_DENOM_P(r), TEMP(0), TEMP(1))) != MP_OK) { in mp_rat_to_decimal()
519 if ((res = mp_int_mul_value(TEMP(1), radix, TEMP(1))) != MP_OK) { in mp_rat_to_decimal()
530 if ((res = mp_int_mul(TEMP(1), TEMP(2), TEMP(1))) != MP_OK) { in mp_rat_to_decimal()
534 if ((res = mp_int_div(TEMP(1), MP_DENOM_P(r), TEMP(1), TEMP(2))) != MP_OK) { in mp_rat_to_decimal()
550 res = mp_int_add_value(TEMP(0), 1, TEMP(0)); in mp_rat_to_decimal()
552 res = mp_int_add_value(TEMP(1), 1, TEMP(1)); in mp_rat_to_decimal()
559 if ((res = mp_int_mul_pow2(TEMP(2), 1, TEMP(2))) != MP_OK) { in mp_rat_to_decimal()
569 res = mp_int_add_value(TEMP(0), 1, TEMP(0)); in mp_rat_to_decimal()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-clrsb.ll22 ; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
25 ; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
40 ; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
42 ; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
57 ; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
60 ; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
75 ; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
77 ; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
H A Darm64-dead-def-frame-index.ll15 ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12
16 ; CHECK: adds [[TEMP]], [[TEMP]], #15
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dipra.ll40 ; DISABLED: mov [[TEMP:r[0-9]+]], r3
43 ; DISABLED: mov r3, [[TEMP]]
58 ; CHECK: mov [[TEMP:r[0-9]+]], r3
60 ; CHECK: mov r3, [[TEMP]]
104 ; CHECK: mov r12, [[TEMP]]
121 ; DISABLED: vmov.f32 s0, [[TEMP]]
136 ; CHECK: vmov.f32 s0, [[TEMP]]
151 ; DISABLED: vmov.f64 d0, [[TEMP]]
166 ; CHECK: vmov.f64 d0, [[TEMP]]
182 ; CHECK: vmov.f32 s0, [[TEMP]]
[all …]
H A Dipra-exact-definition.ll15 ; CHECK: mov [[TEMP:r[0-9]+]], r3
17 ; CHECK: mov r3, [[TEMP]]
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Dencode.mm303 // CHECK-NO-TEMP-SPEC: @[[STR23:.*]] = {{.*}} [3 x i8] c"^v\00"
305 // CHECK-TEMP-SPEC: @[[STR23:.*]] = {{.*}} [13 x i8] c"^{B0<int>=i}\00"
306 // CHECK-TEMP-SPEC: @_ZN32test_cxx_template_specialization3b01E = {{.*}} ([13 x i8], [13 x i8]* @[[…
308 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2d0E = {{.*}} ([3 x i8], [3 x i8]* @[[…
309 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2d1E = {{.*}} ([3 x i8], [3 x i8]* @[[…
310 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2d2E = {{.*}} ([3 x i8], [3 x i8]* @[[…
313 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2s0E = {{.*}} ([3 x i8], [3 x i8]* @[[…
314 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2s1E = {{.*}} ([3 x i8], [3 x i8]* @[[…
317 // CHECK-NO-TEMP-SPEC: @_ZN32test_cxx_template_specialization2u0E = {{.*}} ([3 x i8], [3 x i8]* @[[…
319 // CHECK-NO-TEMP-SPEC: @[[STR26:.*]] = {{.*}} [6 x i8] c"[4^v]\00"
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dlarge-stack.ll46 ; CHECK: ldr [[TEMP:r[0-7]]],
47 ; CHECK: add sp, [[TEMP]]
48 ; CHECK: ldr [[TEMP:r[0-7]]],
49 ; CHECK: add sp, [[TEMP]]
57 ; CHECK: ldr [[TEMP:r[0-7]]],
58 ; CHECK: add sp, [[TEMP]]
68 ; CHECK: ldr [[TEMP:r[0-7]]],
69 ; CHECK: add sp, [[TEMP]]
84 ; CHECK: ldr [[TEMP:r[0-7]]],
85 ; CHECK: add sp, [[TEMP]]
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/
H A Dcrash.ll17 ; ARGPROMOTION-NEXT: [[TEMP:%.*]] = landingpad { i8*, i32 }
65 ; ARGPROMOTION-NEXT: [[TEMP:%.*]] = alloca [[S:%.*]], align 8
67 ; ARGPROMOTION-NEXT: [[TEMP2:%.*]] = call i32 @test_inf_promote_callee(%S* [[TEMP]], %S* [[TEMP1…
82 ; ARGPROMOTION-NEXT: [[TEMP:%.*]] = getelementptr [[S:%.*]], %S* [[ARG1]], i32 0, i32 0
83 ; ARGPROMOTION-NEXT: [[TEMP2:%.*]] = load %S*, %S** [[TEMP]], align 8
H A Dpr42028-recursion.ll12 ; CHECK-NEXT: [[TEMP:%.*]] = alloca [[S:%.*]], align 8
14 ; CHECK-NEXT: [[TEMP2:%.*]] = call i32 @test_inf_promote_callee(%S* [[TEMP]], %S* [[TEMP1]])
28 ; CHECK-NEXT: [[TEMP:%.*]] = getelementptr [[S:%.*]], %S* [[ARG1]], i32 0, i32 0
29 ; CHECK-NEXT: [[TEMP2:%.*]] = load %S*, %S** [[TEMP]], align 8
H A Dstore-after-load.ll8 ; CHECK-NEXT: [[TEMP:%.*]] = load i32, i32* [[ARG]], align 4
9 ; CHECK-NEXT: [[SUM:%.*]] = add i32 [[TEMP]], 1
H A Dbyval.ll12 ; CHECK-NEXT: [[TEMP:%.*]] = add i32 [[B_0]], 1
27 ; CHECK-NEXT: [[TEMP:%.*]] = add i32 [[B_0]], 1
47 ; CHECK-NEXT: [[TEMP:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0
48 ; CHECK-NEXT: [[TEMP1:%.*]] = load i32, i32* [[TEMP]], align 4
50 ; CHECK-NEXT: store i32 [[TEMP2]], i32* [[TEMP]], align 4
66 ; CHECK-NEXT: [[TEMP:%.*]] = add i32 [[B_0]], 1
H A Ddbg.ll27 ; CHECK-NEXT: [[TEMP:%.*]] = getelementptr [[STRUCT_PAIR]], [[STRUCT_PAIR]]* [[P]], i32 0, i32 0
28 ; CHECK-NEXT: store i32* [[TEMP]], i32** [[SINK]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/Coroutines/
H A Dcoro-retcon-once-value2.ll45 ; CHECK-NEXT: [[TEMP:%.*]] = getelementptr inbounds [[F_FRAME:%.*]], %f.Frame* [[FRAMEPTR]], i32…
49 ; CHECK-NEXT: store i32 [[OLDVALUE]], i32* [[TEMP]], align 4
50 …ue { i8*, i32* } { i8* bitcast (void (i8*, i1)* @f.resume.0 to i8*), i32* undef }, i32* [[TEMP]], 1
58 ; CHECK-NEXT: [[TEMP:%.*]] = getelementptr inbounds [[F_FRAME:%.*]], %f.Frame* [[FRAMEPTR]], i32…
63 ; CHECK-NEXT: [[NEWVALUE:%.*]] = load i32, i32* [[TEMP]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/TailCallElim/
H A Dtre-noncapturing-alloca-calls.ll30 ; CHECK-NEXT: [[TEMP:%.*]] = alloca i32, align 4
37 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[TEMP]] to i8*
39 ; CHECK-NEXT: store i32 10, i32* [[TEMP]], align 4
40 ; CHECK-NEXT: call void @_Z15globalIncrementPKi(i32* nonnull [[TEMP]])
H A Dtre-multiple-exits.ll45 ; CHECK-NEXT: [[TEMP:%.*]] = alloca i32, align 4
52 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TEMP]] to i8*
54 ; CHECK-NEXT: call void @_Z11capture_argPi(i32* nonnull [[TEMP]])
/llvm-project-15.0.7/polly/test/Unit/
H A Dlit.cfg32 if 'TEMP' in os.environ:
33 config.environment['TEMP'] = os.environ['TEMP']
/llvm-project-15.0.7/llvm/test/Transforms/MemCpyOpt/
H A Dmemcpy-invoke-memcpy.ll11 ; CHECK-NEXT: [[TEMP:%.*]] = alloca i8, i32 64, align 1
12 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TEMP]], i8* nonnull align 8 [[S…
44 ; CHECK-NEXT: [[TEMP:%.*]] = alloca i8, i32 64, align 1
45 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TEMP]], i8* nonnull align 8 [[S…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsunkaddr-ext.ll24 ; CHECK: movslq %esi, [[TEMP:%[a-z0-9]+]]
25 ; CHECK: movb %dl, (%rdi,[[TEMP]])
/llvm-project-15.0.7/flang/test/Fir/
H A Darray-value-copy.fir107 // CHECK: %[[TEMP:.*]] = fir.allocmem !fir.array<10xi32>
111 // CHECK: %[[COOR1:.*]] = fir.array_coor %[[TEMP]](%{{.*}}) %{{.*}} : (!fir.heap<!fir.arr…
121 // CHECK: %[[COOR1:.*]] = fir.array_coor %[[TEMP]](%{{.*}}) %{{.*}} : (!fir.heap<!fir.arr…
127 // CHECK: %[[COOR0:.*]] = fir.array_coor %[[TEMP]](%{{.*}}) %{{.*}} : (!fir.heap<!fir.arr…
133 // CHECK: fir.freemem %[[TEMP]] : !fir.heap<!fir.array<10xi32>>
179 // CHECK: %[[TEMP:.*]] = fir.allocmem !fir.array<10x5xi32>
214 // CHECK: fir.freemem %[[TEMP]] : !fir.heap<!fir.array<10x5xi32>>
286 // CHECK: %[[TEMP:.*]] = fir.allocmem !fir.array<100xf32>
312 // CHECK: fir.freemem %[[TEMP]] : !fir.heap<!fir.array<100xf32>>
402 // CHECK: %[[TEMP:.*]] = fir.allocmem !fir.array<10xi32>
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-full-partial-split.mlir210 // CHECK: %[[TEMP:.*]] = memref.alloca() {alignment = 32 : i64} : memref<4x8xf32>
221 // CHECK: %[[VAL_15:.*]] = memref.cast %[[TEMP]]
231 // CHECK: %[[CASTED:.*]] = vector.type_cast %[[TEMP]]
256 // LINALG: %[[TEMP:.*]] = memref.alloca() {alignment = 32 : i64} : memref<4x8xf32>
278 // LINALG: %[[VAL_22:.*]] = memref.subview %[[TEMP]]
310 // CHECK: %[[TEMP:.*]] = memref.alloca() {alignment = 32 : i64} : memref<4x8xf32>
323 // CHECK: %[[VAL_16:.*]] = memref.cast %[[TEMP]]
334 // CHECK: %[[VAL_19:.*]] = vector.type_cast %[[TEMP]]
360 // LINALG: %[[TEMP:.*]] = memref.alloca() {alignment = 32 : i64} : memref<4x8xf32>
373 // LINALG: %[[VAL_17:.*]] = memref.cast %[[TEMP]]
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dparameterized_classes.m104 // CHECK: %[[TEMP:.*]] = alloca %[[TY]]*
106 // CHECK: store %[[TY]]* %[[V4]], %[[TY]]** %[[TEMP]]
107 // CHECK: %[[V7:.*]] = bitcast %[[TY]]** %[[TEMP]] to i8**
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Ddce-after-argument-promotion.ll14 ; CHECK-NEXT: [[TEMP:%.*]] = add i32 [[B_0]], 1
15 ; CHECK-NEXT: store i32 [[TEMP]], i32* [[DUMMY]], align 4
/llvm-project-15.0.7/clang/test/Driver/
H A Dcrash-report-crashfile.m5 // RUN: env FORCE_CLANG_DIAGNOSTICS_CRASH= TMPDIR=%t TEMP=%t TMP=%t \
11 // RUN: env TMPDIR=%t TEMP=%t TMP=%t \
/llvm-project-15.0.7/libc/config/windows/
H A DREADME.md8 2. Set TEMP and TMP to a directory. Creating this path is necessary for a
18 Set TEMP and TMP to `C:\src\tmp` or the corresponding path elsewhere.

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