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Searched refs:TBL (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-swizzle-tbl-i16-layout.ll2 ; rdar://13214163 - Make sure we generate a correct lookup table for the TBL
H A Dsve-intrinsics-perm-select.ll1174 ; TBL
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h309 TBL, enumerator
H A DAArch64SchedFalkorDetails.td957 def : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBL(v8i8Three|v16i8Two)$")>;
960 def : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBL(v8i8Four|v16i8Three)$")>;
H A DAArch64SchedCyclone.td611 // TBL,TBX are WriteV.
H A DAArch64ISelLowering.cpp2184 MAKE_CASE(AArch64ISD::TBL) in getTargetNodeName()
4568 return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
10695 SDValue TBL = DAG.getNode(AArch64ISD::TBL, DL, MVT::nxv2i64, V, ShuffleMask); in LowerDUPQLane() local
10696 return DAG.getNode(ISD::BITCAST, DL, VT, TBL); in LowerDUPQLane()
H A DAArch64InstrInfo.td734 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
5444 // AdvSIMD TBL/TBX instructions
5447 defm TBL : SIMDTableLookup< 0, "tbl">;
H A DAArch64InstrFormats.td7632 // AdvSIMD TBL/TBX
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_sve.td1202 // Note: svdup_lane is implemented using the intrinsic for TBL to represent a