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/llvm-project-15.0.7/libcxx/test/std/concepts/concepts.lang/concept.common/
H A Dcommon_with.compile.pass.cpp523 struct T7 {}; struct
525 CommonTypeNoMetaCommonReference(T7);
531 struct common_type<T7, int> {
536 struct common_type<int, T7> {
541 struct common_type<T7&, int&> {
546 struct common_type<int&, T7&> {
551 struct common_type<T7&, const int&> {
556 struct common_type<int&, const T7&> {
561 struct common_type<T7&, volatile int&> {
581 struct common_type<const T7&, int&> {
[all …]
/llvm-project-15.0.7/llvm/utils/unittest/googletest/include/gtest/internal/
H A Dgtest-type-util.h167 typename T6, typename T7>
170 typedef Types6<T2, T3, T4, T5, T6, T7> Tail;
174 typename T6, typename T7, typename T8>
177 typedef Types7<T2, T3, T4, T5, T6, T7, T8> Tail;
184 typedef Types8<T2, T3, T4, T5, T6, T7, T8, T9> Tail;
878 typename T6, typename T7>
894 typename T6, typename T7, typename T8>
1710 GTEST_TEMPLATE_ T7>
1718 GTEST_TEMPLATE_ T7, GTEST_TEMPLATE_ T8>
2540 GTEST_TEMPLATE_ T7>
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/llvm-project-15.0.7/libcxx/test/std/ranges/range.req/range.refinements/
H A Dviewable_range.compile.pass.cpp129 struct T7 : test_range<cpp20_input_iterator> { struct
130 T7(T7 const&) = delete;
132 static_assert(std::ranges::range<T7&>);
133 static_assert(!std::ranges::view<std::remove_cvref_t<T7&>>);
134 static_assert(!std::constructible_from<std::remove_cvref_t<T7&>, T7&>);
136 static_assert(!std::ranges::viewable_range<T7>);
137 static_assert( std::ranges::viewable_range<T7&>);
138 static_assert(!std::ranges::viewable_range<T7&&>);
139 static_assert(!std::ranges::viewable_range<const T7>);
140 static_assert( std::ranges::viewable_range<const T7&>);
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/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dpr52275.ll38 ; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
39 ; CHECK-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 0
49 ; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
72 ; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
73 ; CHECK-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 1
83 ; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
106 ; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
107 ; CHECK-NEXT: [[T8:%.*]] = insertelement <4 x i8> [[T6:%.*]], i8 [[T7]], i64 0
117 ; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
140 ; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8
[all …]
H A Dload-partial-vector-shuffle.ll31 ; SSE-NEXT: [[T7:%.*]] = bitcast <8 x i16> [[VECINIT7_I_I]] to <2 x i64>
32 ; SSE-NEXT: ret <2 x i64> [[T7]]
45 ; AVX-NEXT: [[T7:%.*]] = bitcast <8 x i16> [[VECINIT7_I_I1]] to <2 x i64>
46 ; AVX-NEXT: ret <2 x i64> [[T7]]
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dassembler-with-cpp.c59 #define T7(x) T7 #x macro
61 9: T7(foo)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dand-xor-merge.ll8 ; CHECK-NEXT: [[T7:%.*]] = and i32 [[T61]], [[Z:%.*]]
9 ; CHECK-NEXT: ret i32 [[T7]]
20 ; CHECK-NEXT: [[T7:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
21 ; CHECK-NEXT: ret i32 [[T7]]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-b.ll32 ; CHECK-NEXT: ret i32 [[T7]]
72 ; CHECK-NEXT: ret <8 x i32> [[T7]]
107 ; CHECK-NEXT: ret <8 x i32> [[T7]]
142 ; CHECK-NEXT: ret <8 x i32> [[T7]]
178 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
179 ; CHECK-NEXT: ret i32 [[T7]]
216 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
217 ; CHECK-NEXT: ret i32 [[T7]]
252 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
253 ; CHECK-NEXT: ret i32 [[T7]]
[all …]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-a.ll31 ; CHECK-NEXT: [[T7:%.*]] = and i32 [[TMP2]], 2147483647
32 ; CHECK-NEXT: ret i32 [[T7]]
72 ; CHECK-NEXT: ret <8 x i32> [[T7]]
107 ; CHECK-NEXT: ret <8 x i32> [[T7]]
142 ; CHECK-NEXT: ret <8 x i32> [[T7]]
179 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
180 ; CHECK-NEXT: ret i32 [[T7]]
215 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
216 ; CHECK-NEXT: ret i32 [[T7]]
252 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dcmse-clear-return.c108 typedef struct T7 { struct
110 } T7; typedef
112 T7 t7;
113 __attribute__((cmse_nonsecure_entry)) T7 f7(void) { return t7; } in f7()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-contract-matvec-transforms.mlir69 // CHECK: %[[T7:.*]] = vector.extract %[[T3]][1] : vector<2x2xf32>
71 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<add>} : v…
95 // CHECK: %[[T7:.*]] = vector.extract %[[T3]][1] : vector<2x2xf32>
97 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<maxf>} : …
121 // CHECK: %[[T7:.*]] = vector.extract %[[T1]][1] : vector<2xf32>
122 // CHECK: %[[T8:.*]] = vector.outerproduct %[[T6]], %[[T7]], %[[T5]] {kind = #vector.kind<add>} : v…
146 // CHECK: %[[T7:.*]] = vector.extract %[[T3]][1] : vector<2x2xf32>
148 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<add>} : v…
172 // CHECK: %[[T7:.*]] = vector.extract %[[T1]][1] : vector<2xf32>
173 // CHECK: %[[T8:.*]] = vector.outerproduct %[[T6]], %[[T7]], %[[T5]] {kind = #vector.kind<add>} : v…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dadd.ll160 ; GP32-CMOV: xor $[[T7:[0-9]+]], $[[T5]], $6
320 ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]]
330 ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]]
348 ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5
349 ; MMR3: addu16 $2, $4, $[[T7]]
357 ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]]
358 ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]]
469 ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]]
479 ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]]
509 ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]]
[all …]
H A Dsub.ll131 ; PRE4: subu $[[T7:[0-9]+]], $5, $[[T6]]
132 ; PRE4: subu $[[T8:[0-9]+]], $[[T7]], $[[T5]]
133 ; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]]
149 ; MMR3: lw $[[T7:[0-8]+]], 44($sp)
150 ; MMR3: subu16 $[[T8:[0-9]+]], $5, $[[T7]]
153 ; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]]
174 ; MMR6: lw $[[T7:[0-9]+]], 52($sp)
175 ; MMR6: sltu $[[T8:[0-9]+]], $[[T0]], $[[T7]]
180 ; MMR6: subu16 $[[T13:[0-9]+]], $[[T12]], $[[T7]]
181 ; MMR6: sltu $[[T16:[0-9]+]], $[[T12]], $[[T7]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dfloat-minmax-instruction-flag.ll13 ; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
19 ; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
20 ; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
85 ; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
86 ; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
119 ; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
125 ; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
126 ; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
159 ; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
165 ; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
[all …]
H A Dscalar_after_vectorization.ll17 ; CHECK: %[[T7:.+]] = bitcast i32* %[[T6]] to <4 x i32>*
18 ; CHECK: load <4 x i32>, <4 x i32>* %[[T7]], align 4
31 ; NO-IC: %[[T7:.+]] = sub nsw i64 %[[T5]], %x
33 ; NO-IC: %[[T9:.+]] = getelementptr inbounds i32, i32* %a, i64 %[[T7]]
/llvm-project-15.0.7/llvm/test/Assembler/
H A Dopaque-ptr-struct-types.ll9 ; CHECK-DAG: %T7 = type { i8 }
18 %T7 = type { i8 }
33 declare void @f2(ptr sret(%T7))
/llvm-project-15.0.7/clang/test/Index/
H A Dcomplete-documentation.cpp22 void T7();
28 void T6::T7() { in T7() function in T6
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dtrivial-constructor.cpp32 struct T7 { struct
35 static_assert(!__has_trivial_constructor(T7), "t4 does not have a trivial constructor!"); argument
H A Dtrivial-destructor.cpp32 struct T7 { struct
35 static_assert(!__has_trivial_destructor(T7), "t2 does not have a trivial destructor!"); argument
H A Dundefined-internal.cpp298 class T7 {}; class
315 …Cls2(T7); // expected-warning {{function 'test12::(anonymous namespace)::Cls2::Cls2' has internal…
329 Cls2 obj1((T7())); // expected-note {{used here}} in test()
H A Dattr-mode-tmpl.cpp19 …typedef enum { A7, B7 } __attribute__((mode(V2QI))) T7; // expected-error{{mode 'V2QI' is not supp… in CheckEnumerations() typedef
42 typedef T __attribute__((mode(II))) T7; // expected-error{{unknown machine mode}} in CheckMachineMode() typedef
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dinvalid-eh.ll97 ;T7: entry:
98 ;T7: ret void
99 ;T7: switch1:
101 ;T7: catch1:
102 ;T7: catchpad within %cs1 []
103 ;T7: unreachable
104 ;T7: switch2:
107 ;T7: catch2:
108 ;T7: catchpad within %cs2 []
109 ;T7: unreachable
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dfast-basictest.ll268 ; REASSOC_AND_IC-NEXT: [[T7:%.*]] = fneg fast float [[TMP1]]
269 ; REASSOC_AND_IC-NEXT: ret float [[T7]]
273 ; O2-NEXT: [[T7:%.*]] = fneg fast float [[TMP1]]
274 ; O2-NEXT: ret float [[T7]]
285 ; CHECK-NEXT: [[T7:%.*]] = fneg reassoc nsz float [[TMP1]]
286 ; CHECK-NEXT: ret float [[T7]]
299 ; CHECK-NEXT: [[T7:%.*]] = fsub reassoc float [[T5]], [[A]]
300 ; CHECK-NEXT: ret float [[T7]]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dpromotion_options.mlir18 // CHECK: %[[T7:.+]] = memref.subview %[[ARG0]]
27 // CHECK: memref.copy %[[T7]], %[[T19]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dtwo-entry-phi-return.ll7 ; CHECK-NEXT: [[T7:%.*]] = icmp eq i8* [[M:%.*]], [[N:%.*]]
9 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[T7]], i1 [[T15]], i1 false, !prof [[PROF0:![0-9]…

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