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/llvm-project-15.0.7/libcxx/test/std/concepts/concepts.lang/concept.common/
H A Dcommon_with.compile.pass.cpp400 struct T6 {}; struct
402 CommonTypeNoCommonReference(T6);
408 struct common_type<T6, int> {
413 struct common_type<int, T6> {
418 struct common_type<T6&, int&> {};
421 struct common_type<int&, T6&> {};
424 struct common_type<T6&, const int&> {};
427 struct common_type<int&, const T6&> {};
430 struct common_type<T6&, volatile int&> {};
442 struct common_type<const T6&, int&> {};
[all …]
/llvm-project-15.0.7/libcxx/test/std/ranges/range.req/range.refinements/
H A Dviewable_range.compile.pass.cpp115 struct T6 : test_range<cpp20_input_iterator> { T6(T6&&); T6& operator=(T6&&) = delete; }; struct
116 static_assert( std::ranges::range<T6>);
117 static_assert(!std::ranges::view<T6>);
118 static_assert( std::constructible_from<T6, T6>);
119 static_assert(!std::movable<T6>);
121 static_assert(!std::ranges::viewable_range<T6>);
122 static_assert( std::ranges::viewable_range<T6&>); // lvalue
123 static_assert(!std::ranges::viewable_range<T6&&>);
124 static_assert(!std::ranges::viewable_range<const T6>);
125 static_assert( std::ranges::viewable_range<const T6&>); // lvalue
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/llvm-project-15.0.7/llvm/utils/unittest/googletest/include/gtest/internal/
H A Dgtest-type-util.h160 typename T6>
163 typedef Types5<T2, T3, T4, T5, T6> Tail;
167 typename T6, typename T7>
170 typedef Types6<T2, T3, T4, T5, T6, T7> Tail;
174 typename T6, typename T7, typename T8>
177 typedef Types7<T2, T3, T4, T5, T6, T7, T8> Tail;
184 typedef Types8<T2, T3, T4, T5, T6, T7, T8, T9> Tail;
862 typename T6>
878 typename T6, typename T7>
894 typename T6, typename T7, typename T8>
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/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dunsigned-multiply-overflow-check.ll30 ; SIMPLIFYCFG-NEXT: [[T6:%.*]] = phi i1 [ false, [[BB:%.*]] ], [ [[T4]], [[BB2]] ]
31 ; SIMPLIFYCFG-NEXT: ret i1 [[T6]]
42 ; INSTCOMBINEONLY-NEXT: [[T6:%.*]] = phi i1 [ false, [[BB:%.*]] ], [ [[UMUL_OV]], [[BB2]] ]
43 ; INSTCOMBINEONLY-NEXT: ret i1 [[T6]]
50 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT: [[T6:%.*]] = select i1 [[T0]], i1 false, i1 [[UMUL_OV]]
51 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT: ret i1 [[T6]]
86 ; SIMPLIFYCFG-NEXT: [[T6:%.*]] = phi i1 [ false, [[BB:%.*]] ], [ [[T4]], [[BB2]] ]
87 ; SIMPLIFYCFG-NEXT: [[T7:%.*]] = xor i1 [[T6]], true
101 ; INSTCOMBINEONLY-NEXT: ret i1 [[T6]]
109 ; INSTCOMBINESIMPLIFYCFGONLY-NEXT: [[T6:%.*]] = select i1 [[T0]], i1 true, i1 [[PHI_BO]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbroadcast.ll7 ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroin…
8 ; CHECK-NEXT: ret <4 x float> [[T6]]
21 ; CHECK-NEXT: ret <4 x float> [[T6]]
34 ; CHECK-NEXT: ret <4 x float> [[T6]]
81 ; CHECK-NEXT: ret <4 x float> [[T6]]
96 ; CHECK-NEXT: ret <4 x float> [[T6]]
109 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
110 ; CHECK-NEXT: ret <4 x float> [[T6]]
136 ; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
152 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
[all …]
H A Dbroadcast-inseltpoison.ll7 ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroin…
8 ; CHECK-NEXT: ret <4 x float> [[T6]]
21 ; CHECK-NEXT: ret <4 x float> [[T6]]
34 ; CHECK-NEXT: ret <4 x float> [[T6]]
81 ; CHECK-NEXT: ret <4 x float> [[T6]]
96 ; CHECK-NEXT: ret <4 x float> [[T6]]
109 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
110 ; CHECK-NEXT: ret <4 x float> [[T6]]
136 ; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
152 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
[all …]
H A Dsigned-comparison.ll8 ; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
9 ; CHECK-NEXT: ret i1 [[T6]]
18 ; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
19 ; CHECK-NEXT: ret <4 x i1> [[T6]]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-d.ll30 ; CHECK-NEXT: ret i32 [[T6]]
66 ; CHECK-NEXT: ret <8 x i32> [[T6]]
97 ; CHECK-NEXT: ret <8 x i32> [[T6]]
128 ; CHECK-NEXT: ret <8 x i32> [[T6]]
161 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
162 ; CHECK-NEXT: ret i32 [[T6]]
194 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
195 ; CHECK-NEXT: ret i32 [[T6]]
228 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
229 ; CHECK-NEXT: ret i32 [[T6]]
[all …]
H A Dredundant-left-shift-input-masking-after-truncation-variant-d.ll30 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[TMP1]], [[T3]]
31 ; CHECK-NEXT: ret i32 [[T6]]
68 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
69 ; CHECK-NEXT: ret <8 x i32> [[T6]]
101 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
102 ; CHECK-NEXT: ret <8 x i32> [[T6]]
134 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
135 ; CHECK-NEXT: ret <8 x i32> [[T6]]
170 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
171 ; CHECK-NEXT: ret i32 [[T6]]
H A Dredundant-left-shift-input-masking-after-truncation-variant-a.ll31 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[TMP1]], [[T3]]
32 ; CHECK-NEXT: ret i32 [[T6]]
71 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
72 ; CHECK-NEXT: ret <8 x i32> [[T6]]
106 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
107 ; CHECK-NEXT: ret <8 x i32> [[T6]]
141 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
142 ; CHECK-NEXT: ret <8 x i32> [[T6]]
179 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
180 ; CHECK-NEXT: ret i32 [[T6]]
H A Dredundant-left-shift-input-masking-after-truncation-variant-b.ll31 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[TMP1]], [[T3]]
32 ; CHECK-NEXT: ret i32 [[T6]]
71 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
72 ; CHECK-NEXT: ret <8 x i32> [[T6]]
106 ; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
107 ; CHECK-NEXT: ret <8 x i32> [[T6]]
180 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
181 ; CHECK-NEXT: ret i32 [[T6]]
218 ; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
219 ; CHECK-NEXT: ret i32 [[T6]]
/llvm-project-15.0.7/clang/test/Index/
H A Dcomplete-documentation.cpp20 struct T6 { struct
28 void T6::T7() { in T7()
36 T6 t6; in test1()
H A Dcomplete-documentation-templates.cpp34 void T6();
58 t3.T6(); in test_CC2_CC3_CC4()
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dassembler-with-cpp.c58 #define T6() T6 #nostring macro
60 8: T6()
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dcmse-clear-return.c95 typedef struct T6 { struct
97 } T6; typedef
99 T6 t6;
100 __attribute__((cmse_nonsecure_entry)) T6 f6(void) { return t6; } in f6()
H A Dattr-mode-enums.c27 typedef enum X __attribute__((mode(QI))) T6; in main() typedef
28 T6 x6; in main()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-contract-matvec-transforms.mlir68 // CHECK: %[[T6:.*]] = vector.outerproduct %[[T4]], %[[T5]], %[[T2]] {kind = #vector.kind<add>} : v…
71 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<add>} : v…
94 // CHECK: %[[T6:.*]] = vector.outerproduct %[[T4]], %[[T5]], %[[T2]] {kind = #vector.kind<maxf>} : …
97 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<maxf>} : …
120 // CHECK: %[[T6:.*]] = vector.extract %[[T0]][1] : vector<2x2xf32>
122 // CHECK: %[[T8:.*]] = vector.outerproduct %[[T6]], %[[T7]], %[[T5]] {kind = #vector.kind<add>} : v…
145 // CHECK: %[[T6:.*]] = vector.outerproduct %[[T4]], %[[T5]], %[[T2]] {kind = #vector.kind<add>} : v…
148 // CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<add>} : v…
171 // CHECK: %[[T6:.*]] = vector.extract %[[T0]][1] : vector<2x2xf32>
173 // CHECK: %[[T8:.*]] = vector.outerproduct %[[T6]], %[[T7]], %[[T5]] {kind = #vector.kind<add>} : v…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dadd.ll159 ; GP32-CMOV: sltu $[[T6:[0-9]+]], $[[T5]], $6
188 ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $7
192 ; MMR3: movz $[[T8]], $[[T6]], $[[T9]]
347 ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T3]]
348 ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5
356 ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6
357 ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]]
499 ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $5
500 ; MMR3: addu16 $2, $4, $[[T6]]
508 ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6
[all …]
H A Dsub.ll130 ; PRE4: lw $[[T6:[0-9]+]], 20($sp)
131 ; PRE4: subu $[[T7:[0-9]+]], $5, $[[T6]]
134 ; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]]
148 ; MMR3: movz $[[T6:[0-9]+]], $[[T5]], $[[T3]]
151 ; MMR3: subu16 $[[T9:[0-9]+]], $[[T8]], $[[T6]]
173 ; MMR6: seleqz $[[T6:[0-9]+]], $[[T3]], $[[T5]]
177 ; MMR6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dfloat-minmax-instruction-flag.ll14 ; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
18 ; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
23 ; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]
84 ; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
89 ; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ]
120 ; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
124 ; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
129 ; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]
160 ; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
164 ; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
[all …]
/llvm-project-15.0.7/llvm/test/Assembler/
H A Dopaque-ptr-struct-types.ll8 ; CHECK-DAG: %T6 = type { i8 }
17 %T6 = type { i8 }
29 store ptr getelementptr (%T6, ptr @g, i64 1), ptr %p
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dtrivial-constructor.cpp25 struct T6 { struct
30 static_assert(__has_trivial_constructor(T6), "All nonstatic data members of T6 have trivial constru… argument
H A Dtrivial-destructor.cpp25 struct T6 { struct
30 static_assert(__has_trivial_destructor(T6), "All nonstatic data members of T6 have trivial destruct… argument
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-coalescing.mlir221 // CHECK-DAG: %[[T6:.*]] = affine.apply #[[DIV]](%[[IV]])[%[[T3]]]
222 // CHECK-DAG: %[[J:.*]] = affine.apply #[[MOD]](%[[T6]])[%[[T1]]]
223 // CHECK-DAG: %[[I:.*]] = affine.apply #[[DIV]](%[[T6]])[%[[T1]]]
255 // CHECK-DAG: %[[T6:.*]] = affine.apply #[[IDENTITY]]()[%[[T2]]]
256 // CHECK-DAG: %[[T7:.*]] = affine.apply #[[PRODUCT]](%[[T5]])[%[[T6]]]
258 // CHECK-DAG: %[[K:.*]] = affine.apply #[[MOD]](%[[IV]])[%[[T6]]]
293 // CHECK-DAG: %[[T6:.*]] = affine.apply #[[PRODUCT]](%[[T4]])[%[[T5]]]
294 // CHECK: affine.for %[[IV:.*]] = 0 to %[[T6]]
332 // CHECK-DAG: %[[T6:.*]] = affine.apply #[[IDENTITY]]()[%[[T2]]]
335 // CHECK-DAG: %[[K:.*]] = affine.apply #[[MOD]](%[[IV]])[%[[T6]]]
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dinvalid-eh.ll81 ;T6: entry:
82 ;T6: ret void
83 ;T6: switch1:
86 ;T6: catch1:
87 ;T6: catchpad within %cs1 []
88 ;T6: unreachable
89 ;T6: switch2:
91 ;T6: catch2:
92 ;T6: catchpad within %cs2 []
93 ;T6: unreachable
[all …]

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