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/llvm-project-15.0.7/clang/test/CXX/special/class.inhctor/
H A Dp3.cpp59 template<typename T> struct T4 : B4 { struct
61 template<typename U> T4(U);
63 template<typename T> struct U4 : T4<T> {
64 using T4<T>::T4;
66 T4<void> t4a = {0};
67 T4<void> t4b = {0, 0}; // expected-error {{chosen constructor is explicit}}
/llvm-project-15.0.7/llvm/utils/unittest/googletest/include/gtest/internal/
H A Dgtest-type-util.h150 typedef Types3<T2, T3, T4> Tail;
156 typedef Types4<T2, T3, T4, T5> Tail;
163 typedef Types5<T2, T3, T4, T5, T6> Tail;
170 typedef Types6<T2, T3, T4, T5, T6, T7> Tail;
1688 GTEST_TEMPLATE_ T4>
1691 typedef Templates3<T2, T3, T4> Tail;
1695 GTEST_TEMPLATE_ T4, GTEST_TEMPLATE_ T5>
1698 typedef Templates4<T2, T3, T4, T5> Tail;
2512 GTEST_TEMPLATE_ T4>
2518 typedef Templates4<T1, T2, T3, T4> type;
[all …]
/llvm-project-15.0.7/libcxx/test/std/ranges/range.req/range.refinements/
H A Dviewable_range.compile.pass.cpp72 struct T4 : test_range<cpp20_input_iterator>, std::ranges::view_base { struct
73 T4(T4 const&) = delete;
74 T4(T4&&) = default; // necessary to model view
75 T4& operator=(T4&&) = default; // necessary to model view
77 static_assert(std::ranges::range<T4 const&>);
78 static_assert(std::ranges::view<std::remove_cvref_t<T4 const&>>);
79 static_assert(!std::constructible_from<std::remove_cvref_t<T4 const&>, T4 const&>);
81 static_assert(!std::ranges::viewable_range<T4 const&>);
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dselect-of-bittest.ll13 ; CHECK-NEXT: ret i32 [[T4]]
28 ; CHECK-NEXT: ret <2 x i32> [[T4]]
43 ; CHECK-NEXT: ret <2 x i32> [[T4]]
247 ; CHECK-NEXT: ret i32 [[T4]]
263 ; CHECK-NEXT: ret i32 [[T4]]
491 ; CHECK-NEXT: ret i32 [[T4]]
528 ; CHECK-NEXT: ret i32 [[T4]]
546 ; CHECK-NEXT: ret i32 [[T4]]
580 ; CHECK-NEXT: ret i32 [[T4]]
614 ; CHECK-NEXT: ret i32 [[T4]]
[all …]
H A Dredundant-left-shift-input-masking-variant-a.ll29 ; CHECK-NEXT: ret i32 [[T4]]
54 ; CHECK-NEXT: ret i32 [[T4]]
79 ; CHECK-NEXT: call void @use32(i32 [[T4]])
202 ; CHECK-NEXT: ret i32 [[T4]]
229 ; CHECK-NEXT: call void @use32(i32 [[T4]])
261 ; CHECK-NEXT: call void @use32(i32 [[T4]])
295 ; CHECK-NEXT: ret i32 [[T4]]
320 ; CHECK-NEXT: ret i32 [[T4]]
345 ; CHECK-NEXT: ret i32 [[T4]]
372 ; CHECK-NEXT: ret i32 [[T4]]
[all …]
H A Dredundant-left-shift-input-masking-variant-b.ll28 ; CHECK-NEXT: [[T4:%.*]] = shl i32 [[X]], [[T3]]
29 ; CHECK-NEXT: ret i32 [[T4]]
54 ; CHECK-NEXT: ret i32 [[T4]]
79 ; CHECK-NEXT: call void @use32(i32 [[T4]])
202 ; CHECK-NEXT: ret i32 [[T4]]
229 ; CHECK-NEXT: call void @use32(i32 [[T4]])
261 ; CHECK-NEXT: call void @use32(i32 [[T4]])
295 ; CHECK-NEXT: ret i32 [[T4]]
320 ; CHECK-NEXT: ret i32 [[T4]]
345 ; CHECK-NEXT: ret i32 [[T4]]
[all …]
H A Dicmp-logical.ll617 ; CHECK-NEXT: ret i1 [[T4]]
631 ; CHECK-NEXT: ret i1 [[T4]]
646 ; CHECK-NEXT: ret i1 [[T4]]
660 ; CHECK-NEXT: ret i1 [[T4]]
675 ; CHECK-NEXT: ret i1 [[T4]]
689 ; CHECK-NEXT: ret i1 [[T4]]
949 ; CHECK-NEXT: ret i1 [[T4]]
963 ; CHECK-NEXT: ret i1 [[T4]]
979 ; CHECK-NEXT: ret i1 [[T4]]
993 ; CHECK-NEXT: ret i1 [[T4]]
[all …]
H A Donehot_merge.ll49 ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
50 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]
68 ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
69 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
109 ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
130 ; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]]
131 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
234 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
296 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
357 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]
[all …]
H A Dsigned-truncation-check.ll192 ; CHECK-NEXT: ret <2 x i1> [[T4]]
207 ; CHECK-NEXT: ret <3 x i1> [[T4]]
222 ; CHECK-NEXT: ret <3 x i1> [[T4]]
237 ; CHECK-NEXT: ret <3 x i1> [[T4]]
252 ; CHECK-NEXT: ret <3 x i1> [[T4]]
267 ; CHECK-NEXT: ret <3 x i1> [[T4]]
282 ; CHECK-NEXT: ret <3 x i1> [[T4]]
297 ; CHECK-NEXT: ret <3 x i1> [[T4]]
527 ; CHECK-NEXT: call void @use1(i1 [[T4]])
694 ; CHECK-NEXT: ret i1 [[T4]]
[all …]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-b.ll23 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
28 ; CHECK-NEXT: call void @use32(i32 [[T4]])
30 ; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T4]]
68 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
170 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
175 ; CHECK-NEXT: call void @use32(i32 [[T4]])
207 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
212 ; CHECK-NEXT: call void @use32(i32 [[T4]])
243 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
248 ; CHECK-NEXT: call void @use32(i32 [[T4]])
[all …]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-a.ll23 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
28 ; CHECK-NEXT: call void @use32(i32 [[T4]])
30 ; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T4]]
68 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
170 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
175 ; CHECK-NEXT: call void @use32(i32 [[T4]])
179 ; CHECK-NEXT: [[T7:%.*]] = shl i32 [[T6]], [[T4]]
206 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
211 ; CHECK-NEXT: call void @use32(i32 [[T4]])
242 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
[all …]
H A Dpartally-redundant-left-shift-input-masking-variant-b.ll21 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
25 ; CHECK-NEXT: call void @use32(i32 [[T4]])
26 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]]
56 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
57 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
83 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
84 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
110 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
136 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
141 ; CHECK-NEXT: call void @use32(i32 [[T4]])
[all …]
H A Dpartally-redundant-left-shift-input-masking-variant-a.ll21 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
25 ; CHECK-NEXT: call void @use32(i32 [[T4]])
26 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], [[T4]]
56 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
57 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
83 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
84 ; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[X:%.*]], [[T4]]
110 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
136 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
141 ; CHECK-NEXT: call void @use32(i32 [[T4]])
[all …]
H A Dredundant-left-shift-input-masking-after-truncation-variant-b.ll23 ; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]]
29 ; CHECK-NEXT: call void @use64(i64 [[T4]])
69 ; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T4]])
104 ; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T4]])
139 ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T4]])
172 ; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]]
178 ; CHECK-NEXT: call void @use64(i64 [[T4]])
179 ; CHECK-NEXT: [[T5:%.*]] = trunc i64 [[T4]] to i32
209 ; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]]
215 ; CHECK-NEXT: call void @use64(i64 [[T4]])
[all …]
H A Dpartally-redundant-left-shift-input-masking-variant-d.ll25 ; CHECK-NEXT: [[T4:%.*]] = and i32 [[TMP1]], 2147483647
26 ; CHECK-NEXT: ret i32 [[T4]]
52 ; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 21474836…
53 ; CHECK-NEXT: ret <8 x i32> [[T4]]
75 ; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], <i32 2147483647, i32 2147483647, i32 21474836…
76 ; CHECK-NEXT: ret <8 x i32> [[T4]]
98 ; CHECK-NEXT: [[T4:%.*]] = and <8 x i32> [[TMP1]], <i32 poison, i32 1, i32 2147483647, i32 -1, i…
99 ; CHECK-NEXT: ret <8 x i32> [[T4]]
124 ; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
125 ; CHECK-NEXT: ret i32 [[T4]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dadd.ll181 ; GP64: daddu $2, $[[T0]], $[[T4]]
186 ; MMR3-DAG: lw $[[T4:[0-9]+]], 36($sp)
315 ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]]
316 ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6
321 ; PRE4: move $4, $[[T4]]
354 ; MMR6: selnez $[[T4:[0-9]+]], $[[T2]], $[[T3]]
358 ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]]
464 ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]]
465 ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6
470 ; PRE4: move $4, $[[T4]]
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dfp-intrinsics.ll4 ; RUN: sed -e s/.T4:// %s | not opt -verify -disable-output 2>&1 | FileCheck --check-prefix=CHECK4 …
60 ;T4: define double @f4(double %a) #0 {
61 ;T4: entry:
62 ;T4: %fadd = call double @llvm.experimental.constrained.sqrt.f64(
63 ;T4: double %a,
64 ;T4: metadata !"round.dynomite",
65 ;T4: metadata !"fpexcept.strict") #0
66 ;T4: ret double %fadd
67 ;T4: }
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dpr52275.ll36 ; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1
37 ; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
48 ; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
70 ; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1
71 ; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
82 ; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
104 ; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1
105 ; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
116 ; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
139 ; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dvirtual-override.cpp45 namespace T4 { namespace
57 struct T4::b -> struct T4::a\n\
58 struct T4::b -> struct T4::a1 -> struct T4::a)}}
H A Dtrivial-constructor.cpp17 struct T4 : virtual T3 { struct
19 static_assert(!__has_trivial_constructor(T4), "T4 has a virtual base class!");
33 T4 t4;
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Darc-unsafeclaim.m37 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
66 // CHECK-NEXT: store i8* [[T4]], i8** [[Y]]
67 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
92 // CHECK-NEXT: store i8* [[T4]], i8** [[Y]]
94 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
124 // CHECK-NEXT: store i8* [[T4]], i8** [[Y]]
126 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
152 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
175 // CHECK-NEXT: store i8* [[T4]], i8** [[X]]
176 // CHECK-NEXT: store i8* [[T4]], i8** [[Y]]
[all …]
H A Darc-weak-property.m23 // CHECK-NEXT: [[T4:%.*]] = bitcast i8* [[T3]] to i8**
24 // CHECK-NEXT: [[T5:%.*]] = call i8* @llvm.objc.loadWeakRetained(i8** [[T4]])
40 // CHECK-NEXT: [[T4:%.*]] = bitcast i8* [[T3]] to i8**
41 // CHECK-NEXT: call i8* @llvm.objc.storeWeak(i8** [[T4]], i8* [[V]])
53 // CHECK-NEXT: [[T4:%.*]] = bitcast i8* [[T3]] to i8**
54 // CHECK-NEXT: call void @llvm.objc.destroyWeak(i8** [[T4]])
/llvm-project-15.0.7/mlir/test/Conversion/VectorToLLVM/
H A Dvector-mask-to-llvm.mlir10 // CMP32: %[[T4:.*]] = arith.cmpi slt, %[[T0]], %[[T3]] : vector<11xi32>
11 // CMP32: return %[[T4]] : vector<11xi1>
19 // CMP64: %[[T4:.*]] = arith.cmpi slt, %[[T0]], %[[T3]] : vector<11xi64>
20 // CMP64: return %[[T4]] : vector<11xi1>
33 // CMP32: %[[T4:.*]] = arith.cmpi slt, %[[T0]], %[[T3]] : vector<[11]xi32>
34 // CMP32: return %[[T4]] : vector<[11]xi1>
42 // CMP64: %[[T4:.*]] = arith.cmpi slt, %[[T0]], %[[T3]] : vector<[11]xi64>
43 // CMP64: return %[[T4]] : vector<[11]xi1>
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_syscall_linux_x86_64.inc46 template <typename T1, typename T2, typename T3, typename T4>
47 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4) {
56 template <typename T1, typename T2, typename T3, typename T4, typename T5>
57 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4,
68 template <typename T1, typename T2, typename T3, typename T4, typename T5,
70 static uptr internal_syscall(u64 nr, T1 arg1, T2 arg2, T3 arg3, T4 arg4,
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dcmse-clear-return.c69 typedef struct T4 { struct
71 } T4; typedef
73 T4 t4;
74 __attribute__((cmse_nonsecure_entry)) T4 f4(void) { return t4; } in f4()

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