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Searched refs:SuccPred (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineBlockPlacement.cpp857 if (SuccPred == Succ || SuccPred == BB in isProfitableToTailDup()
858 || BlockToChain[SuccPred] == &Chain in isProfitableToTailDup()
861 auto Freq = MBFI->getBlockFreq(SuccPred) in isProfitableToTailDup()
862 * MBPI->getEdgeProbability(SuccPred, Succ); in isProfitableToTailDup()
968 for (auto *SuccPred : Succ->predecessors()) { in isTrellis() local
970 if (Successors.count(SuccPred)) { in isTrellis()
978 if (SuccPred == BB || (BlockFilter && !BlockFilter->count(SuccPred)) || in isTrellis()
983 if (!SeenPreds.insert(SuccPred).second) in isTrellis()
985 if (!hasSameSuccessors(*SuccPred, Successors)) in isTrellis()
1069 if (SuccPred != BB) in getBestTrellisSuccessor()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp2865 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse() local
2866 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()
2870 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
2871 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()
2879 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
2880 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()