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Searched refs:SubsumesPredicate (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h235 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DHexagonInstrInfo.cpp1715 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate() function in HexagonInstrInfo
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h612 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DPPCInstrInfo.cpp2288 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate() function in PPCInstrInfo
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h174 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
H A DARMBaseInstrInfo.cpp632 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate() function in ARMBaseInstrInfo
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1467 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate() function
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DIfConversion.cpp1185 if (BBI.Predicate.size() && !TII->SubsumesPredicate(Pred, BBI.Predicate)) in FeasibilityAnalysis()
1200 !TII->SubsumesPredicate(Cond, RevPred)) in FeasibilityAnalysis()