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/llvm-project-15.0.7/llvm/test/TableGen/
H A DConcatenatedSubregs.td22 def sub0 : SubRegIndex<32>;
23 def sub1 : SubRegIndex<32, 32>;
24 def sub2 : SubRegIndex<32, 64>;
26 def ssub0 : SubRegIndex<16>;
27 def ssub1 : SubRegIndex<16, 16>;
91 // CHECK-LABEL: SubRegIndex sub0:
92 // CHECK-LABEL: SubRegIndex sub1:
93 // CHECK-LABEL: SubRegIndex sub2:
95 // CHECK: SubRegIndex ssub1_ssub2:
96 // CHECK: SubRegIndex ssub3_ssub4:
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H A Dambiguous-composition.td3 // CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Tes…
4 // CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::s…
16 def subreg_l32 : SubRegIndex<32, 0>;
17 def subreg_h32 : SubRegIndex<32, 32>;
18 def subreg_h64 : SubRegIndex<64, 64>;
19 def subreg_l64 : SubRegIndex<64, 0>;
H A DGlobalISelEmitterRegSequence.td17 def sub0 : SubRegIndex<16>;
18 def sub1 : SubRegIndex<16, 16>;
55 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
57 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
71 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
73 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
H A DRegisterInfoEmitter-regcost-tuple.td19 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
26 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
28 !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
29 !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
H A DGlobalISelEmitter-nested-subregs.td8 def lo8 : SubRegIndex<8>;
9 def hi8 : SubRegIndex<8, 8>;
10 def lo16 : SubRegIndex<16>;
11 def hi16 : SubRegIndex<16, 16>;
H A Dbare-minimum-psets.td14 def sub0 : SubRegIndex<32>;
15 def sub1 : SubRegIndex<32, 32>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
225 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIRegisterInfo.td25 def lo16 : SubRegIndex<16, 0>;
26 def hi16 : SubRegIndex<16, 16>;
29 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
41 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
56 list<SubRegIndex> ret2 = [sub0, sub1];
57 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
58 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
59 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4];
63 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3,
67 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3,
[all …]
H A DSIInstructions.td1097 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
1101 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
1110 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1113 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
1117 f32, v3f32, Index, !cast<SubRegIndex>(sub#Index)
1120 f32, v3f32, Index, !cast<SubRegIndex>(sub#Index)
1126 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1129 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
1133 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
1136 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
[all …]
H A DR600.td24 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.td50 def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63)
51 def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31)
52 def sub_even : SubRegIndex<64>; // High 64 bit (0..63)
53 def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127)
54 def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255)
55 def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511)
/llvm-project-15.0.7/llvm/test/TableGen/Common/
H A Dreg-with-subregs-common.td23 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
32 !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
33 !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<64>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def sube64 : SubRegIndex<64>;
39 def dsub0 : SubRegIndex<64>;
40 def dsub1 : SubRegIndex<64>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td17 list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX,
28 def MxSubRegIndex8Lo : SubRegIndex<8, 0>;
29 def MxSubRegIndex16Lo : SubRegIndex<16, 0>;
73 class MxPseudoReg<string N, list<Register> SUBREGS = [], list<SubRegIndex> SUBIDX = []>
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td24 def sub_16 : SubRegIndex<16>;
36 def sub_32 : SubRegIndex<32>;
54 def sub_vrm4_0 : SubRegIndex<256>;
55 def sub_vrm4_1 : SubRegIndex<256, 256>;
56 def sub_vrm2_0 : SubRegIndex<128>;
57 def sub_vrm2_1 : SubRegIndex<128, 128>;
60 def sub_vrm1_0 : SubRegIndex<64>;
61 def sub_vrm1_1 : SubRegIndex<64, 64>;
69 def sub_32_hi : SubRegIndex<32, 32>;
352 // Generate [start, end) SubRegIndex list.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td13 def sub_32 : SubRegIndex<32>;
14 def sub_64 : SubRegIndex<64>;
15 def sub_lo : SubRegIndex<32>;
16 def sub_hi : SubRegIndex<32, 32>;
17 def sub_dsp16_19 : SubRegIndex<4, 16>;
18 def sub_dsp20 : SubRegIndex<1, 20>;
19 def sub_dsp21 : SubRegIndex<1, 21>;
20 def sub_dsp22 : SubRegIndex<1, 22>;
21 def sub_dsp23 : SubRegIndex<1, 23>;
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td27 def sub32_0 : SubRegIndex<32, 0>;
28 def sub32_32 : SubRegIndex<32, 32>;
29 def sub64_0 : SubRegIndex<64, 0>;
30 def sub64_64 : SubRegIndex<64,64>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td37 def qqsub_0 : SubRegIndex<256>;
38 def qqsub_1 : SubRegIndex<256, 256>;
41 def qsub_0 : SubRegIndex<128>;
42 def qsub_1 : SubRegIndex<128, 128>;
46 def dsub_0 : SubRegIndex<64>;
47 def dsub_1 : SubRegIndex<64, 64>;
55 def ssub_0 : SubRegIndex<32>;
56 def ssub_1 : SubRegIndex<32, 32>;
72 def gsub_0 : SubRegIndex<32>;
73 def gsub_1 : SubRegIndex<32, 32>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td23 def sub_8bit : SubRegIndex<8>;
24 def sub_8bit_hi : SubRegIndex<8, 8>;
25 def sub_8bit_hi_phony : SubRegIndex<8, 8>;
26 def sub_16bit : SubRegIndex<16>;
27 def sub_16bit_hi : SubRegIndex<16, 16>;
28 def sub_32bit : SubRegIndex<32>;
29 def sub_xmm : SubRegIndex<128>;
30 def sub_ymm : SubRegIndex<256>;
31 def sub_mask_0 : SubRegIndex<-1>;
32 def sub_mask_1 : SubRegIndex<-1, -1>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td13 def sub_lt : SubRegIndex<1>;
14 def sub_gt : SubRegIndex<1, 1>;
15 def sub_eq : SubRegIndex<1, 2>;
16 def sub_un : SubRegIndex<1, 3>;
17 def sub_32 : SubRegIndex<32>;
18 def sub_64 : SubRegIndex<64>;
19 def sub_vsx0 : SubRegIndex<128>;
20 def sub_vsx1 : SubRegIndex<128, 128>;
21 def sub_gp8_x0 : SubRegIndex<64>;
22 def sub_gp8_x1 : SubRegIndex<64, 64>;
H A DPPCRegisterInfoMMA.td15 def sub_pair0 : SubRegIndex<256>;
16 def sub_pair1 : SubRegIndex<256, 256>;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td118 def isub_lo : SubRegIndex<32>;
119 def isub_hi : SubRegIndex<32, 32>;
120 def vsub_lo : SubRegIndex<512>;
121 def vsub_hi : SubRegIndex<512, 512>;
122 def vsub_fake: SubRegIndex<512>;
123 def wsub_lo : SubRegIndex<1024>;
124 def wsub_hi : SubRegIndex<1024, 1024>;
125 def subreg_overflow : SubRegIndex<1, 0>;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td23 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
24 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
25 def subreg_l64 : SubRegIndex<64, 0>;
26 def subreg_h64 : SubRegIndex<64, 64>;
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td24 def sub_even : SubRegIndex<32>;
25 def sub_odd : SubRegIndex<32, 32>;
26 def sub_even64 : SubRegIndex<64>;
27 def sub_odd64 : SubRegIndex<64, 64>;

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