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Searched refs:Strided (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h140 uint16_t Strided : 1; member
161 uint16_t Strided : 1; member
180 uint16_t Strided : 1; member
189 uint16_t Strided : 1; member
H A DRISCVInstrInfoVPseudos.td468 bits<1> Strided = Str;
485 bits<1> Strided = Str;
495 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
534 bits<1> Strided = Str;
571 bits<1> Strided = Str;
840 RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
853 RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
865 RISCVVSE</*Masked*/0, /*Strided*/1, log2<EEW>.val, VLMul> {
878 RISCVVSE</*Masked*/1, /*Strided*/1, log2<EEW>.val, VLMul> {
4405 // 7.5 Vector Strided Instructions
[all …]
H A DRISCVScheduleV.td22 // 7.4.1. Vector Unit-Strided Mask
25 // 7.5. Vector Strided Instructions
280 // 7.4.1. Vector Unit-Strided Mask
282 // 7.5. Vector Strided Instructions
H A DRISCVInstrInfoV.td126 // Strided Segment Loads and Stores
853 // Vector Strided Instructions
901 // Vector Strided Instructions
1535 // Vector Strided Instructions
1573 // Vector Strided Segment Instructions
/llvm-project-15.0.7/mlir/include/mlir/IR/
H A DBuiltinTypes.td493 ##### Strided MemRef
522 Strided memrefs represent a view abstraction over preallocated data. They
523 are constructed with special ops, yet to be introduced. Strided memrefs are
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dnormalize-memrefs.mlir97 // Strided, but the strides are in the linearized space.
/llvm-project-15.0.7/mlir/docs/Dialects/Linalg/
H A D_index.md503 [Strided MemRef (a.k.a View)](https://groups.google.com/a/tensorflow.org/forum/#!topic/mlir/MaL8m2n…
505 *Strided MemRef*. In the future we expect to use other structured data types and
/llvm-project-15.0.7/mlir/include/mlir/Dialect/LLVMIR/
H A DLLVMIntrinsicOps.td615 // Strided load/store
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/IR/
H A DAffineOps.td944 dimensions of the shape. Strided vector loads will be supported in the future.
1010 respective dimensions of the shape. Strided vector stores will be supported
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Ddma-generate.mlir187 // Strided DMA here: 32 x 32 tile in a 256 x 1024 memref.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td1502 // Strided loads/stores for fixed vectors.
/llvm-project-15.0.7/mlir/docs/Rationale/
H A DRationaleLinalgDialect.md96 - the `!linalg.view` type folded into the *"Strided MemRef"* type while
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Driscv_vector.td1593 // 7.5. Vector Strided Instructions