Searched refs:SrcReg0Sub1 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6735 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
6739 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
6796 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub() local
6813 .add(SrcReg0Sub1) in splitScalar64BitAddSub()
6864 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
6880 .add(SrcReg0Sub1) in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 4085 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm( in EmitInstrWithCustomInserter() local
4101 .add(SrcReg0Sub1) in EmitInstrWithCustomInserter()
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