Searched refs:SrcReg0Sub0 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6725 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
6733 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
6790 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub() local
6805 .add(SrcReg0Sub0) in splitScalar64BitAddSub()
6860 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
6875 .add(SrcReg0Sub0) in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 4080 MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm( in EmitInstrWithCustomInserter() local
4093 .add(SrcReg0Sub0) in EmitInstrWithCustomInserter()
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