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Searched refs:SrcRB (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp635 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping() local
637 DstRB = SrcRB; in getInstrMapping()
638 else if (!SrcRB) in getInstrMapping()
639 SrcRB = DstRB; in getInstrMapping()
642 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
645 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
646 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
661 const RegisterBank &SrcRB = in getInstrMapping() local
664 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
665 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
H A DAArch64InstructionSelector.cpp2642 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
2644 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2646 if (SrcRB.getID() == AArch64::GPRRegBankID) { in select()
3070 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in select() local
3072 if (DstRB.getID() != SrcRB.getID()) { in select()
3083 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(SrcTy, SrcRB); in select()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp722 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt() local
724 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
731 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
851 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext() local
853 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
860 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1927 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_TRUNC() local
1932 DstRB = SrcRB; in selectG_TRUNC()
1935 if (SrcRB != DstRB) in selectG_TRUNC()
1945 TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB); in selectG_TRUNC()
2556 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_PTRMASK() local
2559 if (DstRB != SrcRB) // Should only happen for hand written MIR. in selectG_PTRMASK()
2585 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); in selectG_PTRMASK()
2692 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT() local
2701 TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB); in selectG_EXTRACT_VECTOR_ELT()
2719 if (SrcRB->getID() == AMDGPU::SGPRRegBankID) { in selectG_EXTRACT_VECTOR_ELT()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1010 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1014 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()