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Searched refs:Src2Reg (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp105 Register Src2Reg = MBBI->getOperand(2).getReg(); in selectSELRMux() local
108 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
126 Src2Reg = DestReg; in selectSELRMux()
132 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
134 std::swap(Src1Reg, Src2Reg); in selectSELRMux()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
319 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
321 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
327 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
335 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
337 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
354 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
356 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
364 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
365 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
[all …]
H A DHexagonMCCompound.cpp81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
102 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp3388 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3404 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
3886 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
4025 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4027 isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
4041 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4059 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4069 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4070 if (isDblRegForSubInst(Src2Reg, HRI) && in getDuplexCandidateGroup()
4145 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp276 Register Src2Reg = MI->getOperand(3).getReg(); in ExpandFPMLxInstruction() local
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1791 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorSHL() local
1824 Shl.addUse(Src2Reg); in selectVectorSHL()
1837 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorAshrLshr() local
1881 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg}); in selectVectorAshrLshr()
3779 Register Src2Reg = I.getOperand(3).getReg(); in selectVectorICmp() local
3928 std::swap(SrcReg, Src2Reg); in selectVectorICmp()
3930 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg}); in selectVectorICmp()
3989 Register Src2Reg = I.getOperand(2).getReg(); in selectMergeValues() local
5132 Register Src2Reg = I.getOperand(2).getReg(); in selectShuffleVector() local
5133 const LLT Src2Ty = MRI.getType(Src2Reg); in selectShuffleVector()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2637 Register Src2Reg = getRegForValue(Src2Val); in optimizeSelect() local
2638 if (!Src2Reg) in optimizeSelect()
2645 Src2Reg); in optimizeSelect()
2757 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
2759 if (!Src1Reg || !Src2Reg) in selectSelect()
2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
2765 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); in selectSelect()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1039 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1058 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp4455 Register Src2Reg = PtrAdd.getOperand(2).getReg(); in reassociationCanBreakAddressingModePattern() local
4463 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in reassociationCanBreakAddressingModePattern()
4576 Register Src2Reg = MI.getOperand(2).getReg(); in matchReassocFoldConstantsInSubTree() local
4582 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in matchReassocFoldConstantsInSubTree()
4587 auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2); in matchReassocFoldConstantsInSubTree()
H A DLegalizerHelper.cpp4261 Register Src2Reg = MI.getOperand(2).getReg(); in fewerElementsVectorShuffle() local
4265 LLT Src2Ty = MRI.getType(Src2Reg); in fewerElementsVectorShuffle()
4283 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); in fewerElementsVectorShuffle()
4933 Register Src2Reg = MI.getOperand(2).getReg(); in moreElementsVectorShuffle() local
4937 LLT Src2Ty = MRI.getType(Src2Reg); in moreElementsVectorShuffle()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3794 MCRegister Src2Reg = Src2.getReg(); in validateMFMA() local
3796 if (Src2Reg == DstReg) in validateMFMA()
3803 if (TRI->regsOverlap(Src2Reg, DstReg)) { in validateMFMA()
3804 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands), in validateMFMA()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9915 Register Src2Reg = MI.getOperand(2).getReg(); in emitQuietFCMP() local
9925 .addReg(Src2Reg); in emitQuietFCMP()
9936 .addReg(Src2Reg, getKillRegState(MI.getOperand(2).isKill())); in emitQuietFCMP()