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Searched refs:Src0VT (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DVOPInstructions.td1096 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers));
1123 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1128 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1132 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))];
1141 …(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1147 …(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1148 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
1152 … (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))];
1170 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp),
1171 (VOP3Mods0 P.Src0VT:$src0))
[all …]
H A DSIInstrInfo.td2283 !if(!eq(Src0VT.Size, 64),
2300 !if(!eq(Src0VT.Size, 64),
2360 !if(!eq(Src0VT.Size, 64),
2387 field ValueType Src0VT = ArgVT[1];
2410 field Operand Src0ModDPP = getSrcModDPP<Src0VT>.ret;
2414 field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
2423 field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
2428 field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
2433 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
2445 field bit IsPacked = isPackedType<Src0VT>.ret;
[all …]
H A DVOP3PInstructions.td739 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)),
743 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
748 (P.Src0VT P.Src0VT:$src0),
752 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
757 (DotIUVOP3PMods i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0),
761 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
103 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
105 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
107 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP3Instructions.td801 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
802 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
803 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
810 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
811 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
812 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
H A DVOPCInstructions.td53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
97 let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
122 let ReadsModeReg = isFloatType<P.Src0VT>.ret;
229 (setcc (P.Src0VT
231 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
232 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
235 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
754 (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers)),
H A DVOP2Instructions.td72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
125 (node (P.Src0VT
127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
703 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
712 (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp2822 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
2832 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
2845 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()