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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1704963983.ll27 %L5 = load i8, i8* %Sl
28 store i8 %L, i8* %Sl
45 %L18 = load i8, i8* %Sl
46 store i8 -1, i8* %Sl
57 %L26 = load i8, i8* %Sl
68 %L33 = load i8, i8* %Sl
69 store i8 %L26, i8* %Sl
76 %L40 = load i8, i8* %Sl
89 store i8 77, i8* %Sl
128 store i8 %L, i8* %Sl
[all …]
H A Dllvm-stress-s3997499501.ll25 %L5 = load double, double* %Sl
37 %L11 = load double, double* %Sl
38 store double 0.000000e+00, double* %Sl
52 %L18 = load double, double* %Sl
53 store double 0.000000e+00, double* %Sl
63 %L24 = load double, double* %Sl
75 store double %L5, double* %Sl
98 %L43 = load double, double* %Sl
113 store double %L43, double* %Sl
148 store double %Sl48, double* %Sl
[all …]
H A Dllvm-stress-s525530439.ll24 %Sl = select i1 true, i16 -1, i16 -11642
38 %I14 = insertelement <1 x i16> zeroinitializer, i16 %Sl, i32 0
75 %Cmp39 = icmp sgt i16 -11642, %Sl
96 %I48 = insertelement <1 x i16> %Shuff42, i16 %Sl, i32 0
128 %I69 = insertelement <4 x i16> %Shuff47, i16 %Sl, i32 3
H A Dllvm-stress-s1935737938.ll24 %Sl = select i1 true, <1 x i64> <i64 -1>, <1 x i64> <i64 -1>
37 %Shuff13 = shufflevector <1 x i64> %Sl, <1 x i64> <i64 -1>, <1 x i32> <i32 1>
47 %E19 = extractelement <1 x i64> %Sl, i32 0
H A Dllvm-stress-s3861334421.ll24 …%Sl = select i1 false, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8>…
29 %I8 = insertelement <8 x i8> %Sl, i8 7, i32 4
109 %B60 = udiv <8 x i8> %Sl, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
H A Dllvm-stress-s997348632.ll23 %Sl = select i1 false, <4 x i64> %Shuff, <4 x i64> %Shuff
47 %E19 = extractelement <4 x i64> %Sl, i32 3
H A Dllvm-stress-s3926023935.ll23 %Sl = select i1 false, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
112 %I58 = insertelement <2 x i32> %Sl, i32 %Tr52, i32 0
H A Dllvm-stress-s2704903805.ll23 %Sl = select i1 true, float 0.000000e+00, float 0x401E76A240000000
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A DsplitMove_undefReg_mverifier.ll25 %L5 = load i64, i64* %Sl
45 %Sl17 = select i1 %E, i64* %Sl, i64* %Sl
51 store i64 0, i64* %Sl
77 store i64 %L5, i64* %Sl
84 %L37 = load i64, i64* %Sl
85 store i64 %L5, i64* %Sl
108 %L50 = load i64, i64* %Sl
123 store i64 %L5, i64* %Sl
138 store i64 %L37, i64* %Sl
150 store i64 %L73, i64* %Sl
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Dfill-trap-ppc.s5 # RUN: llvm-readelf -Sl %t.ppc64le | FileCheck %s
10 # RUN: llvm-readelf -Sl %t.ppc64 | FileCheck %s
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dstd-unal-fi.ll58 %Sl = select i1 false, <16 x float>* %A, <16 x float>* %A
68 store <16 x float> zeroinitializer, <16 x float>* %Sl
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpr49076.ll34 %Sl = select i1 %L1, <4 x i64> %Se, <4 x i64> zeroinitializer
H A Dliveness-local-regalloc.ll81 %Sl = select i1 true, <2 x i8> %I, <2 x i8> <i8 -1, i8 -1>
H A Dfold-vector-shuffle-crash.ll32 %Sl = select i1 false, <4 x i64> zeroinitializer, <4 x i64> zeroinitializer
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon.td1423 def SCALAR_SCVTFD : SInst<"vcvt_f64", "(1F)(1!)", "Sl">;
1470 def SCALAR_CMGE : SInst<"vcge", "(U1)11", "Sl">;
1471 def SCALAR_CMGEZ : SInst<"vcgez", "(U1)1", "Sl">;
1474 def SCALAR_CMLEZ : SInst<"vclez", "(U1)1", "Sl">;
1476 def SCALAR_CMLTZ : SInst<"vcltz", "(U1)1", "Sl">;
1477 def SCALAR_CMGT : SInst<"vcgt", "(U1)11", "Sl">;
1478 def SCALAR_CMGTZ : SInst<"vcgtz", "(U1)1", "Sl">;
1507 def SCALAR_ABS : SInst<"vabs", "11", "Sl">;
1519 def SCALAR_NEG : SInst<"vneg", "11", "Sl">;
/llvm-project-15.0.7/compiler-rt/cmake/Modules/
H A DAddCompilerRT.cmake736 set(strip_command COMMAND xcrun strip -Sl $<TARGET_FILE:${name}>)
/llvm-project-15.0.7/llvm/tools/llvm-objdump/
H A DMachODump.cpp10208 MachO::sub_library_command Sl = Obj->getSubLibraryCommand(Command); in PrintLoadCommands() local
10209 PrintSubLibraryCommand(Sl, Command.Ptr); in PrintLoadCommands()