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Searched refs:SingleIssue (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td90 let SingleIssue = 1;
165 let SingleIssue = 1;
191 let SingleIssue = 1;
285 let SingleIssue = 1;
295 let SingleIssue = 1;
299 let SingleIssue = 1;
435 def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
436 def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
H A DARMSubtarget.h146 SingleIssue, enumerator
197 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
H A DARMScheduleR52.td723 let SingleIssue = 1;
729 let SingleIssue = 1;
735 let SingleIssue = 1;
H A DARMBaseInstrInfo.cpp3837 case ARMSubtarget::SingleIssue: in getNumMicroOps()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td261 // SingleIssue is an alias for Begin/End Group.
262 bit SingleIssue = false;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td96 def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1;…