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Searched refs:Sign (Results 1 – 25 of 146) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Support/
H A DLEB128.cpp31 int Sign = Value >> (8 * sizeof(Value) - 1); in getSLEB128Size() local
37 IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0; in getSLEB128Size()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DCmpInstAnalysis.cpp40 Constant *llvm::getPredForICmpCode(unsigned Code, bool Sign, Type *OpTy, in getPredForICmpCode() argument
46 case 1: Pred = Sign ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; in getPredForICmpCode()
48 case 3: Pred = Sign ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; in getPredForICmpCode()
49 case 4: Pred = Sign ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; in getPredForICmpCode()
51 case 6: Pred = Sign ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; in getPredForICmpCode()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DBCD.h37 uint8_t Sign = Ptr[ByteLen - 1] & 0x0f; variable
39 if (Sign == 0x0d || Sign == 0x0b)
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h647 uint8_t Sign = (Imm >> 7) & 0x1; in getFPImmFloat() local
656 I |= Sign << 31; in getFPImmFloat()
668 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1; in getFP16Imm() local
683 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP16Imm()
706 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; in getFP32Imm() local
723 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP32Imm()
734 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; in getFP64Imm() local
751 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP64Imm()
/llvm-project-15.0.7/clang/lib/Basic/
H A DTargetID.cpp88 auto Sign = Splits.first.back(); in parseTargetIDWithFormatCheckingOnly() local
90 if (Sign != '+' && Sign != '-') in parseTargetIDWithFormatCheckingOnly()
92 bool IsOn = Sign == '+'; in parseTargetIDWithFormatCheckingOnly()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h347 uint8_t Sign = (Imm >> 7) & 0x1; in getFPImmFloat() local
357 I |= Sign << 31; in getFPImmFloat()
369 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1; in getFP16Imm() local
384 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP16Imm()
395 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; in getFP32Imm() local
412 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP32Imm()
423 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; in getFP64Imm() local
440 return ((int)Sign << 7) | (Exp << 4) | Mantissa; in getFP64Imm()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dand-06.ll58 ; Sign extension to 32 bits, negative constant.
71 ; Sign extension to 64 bits, negative constant.
84 ; Sign extension to 32 bits, positive constant.
97 ; Sign extension to 64 bits, positive constant.
H A Dor-06.ll58 ; Sign extension to 32 bits, negative constant.
71 ; Sign extension to 64 bits, negative constant.
84 ; Sign extension to 32 bits, positive constant.
97 ; Sign extension to 64 bits, positive constant.
H A Dxor-06.ll58 ; Sign extension to 32 bits, negative constant.
71 ; Sign extension to 64 bits, negative constant.
84 ; Sign extension to 32 bits, positive constant.
97 ; Sign extension to 64 bits, positive constant.
H A Dargs-05.ll16 ; Sign extension of something that is already sign-extended.
27 ; Sign extension of something that is already zero-extended.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMMachineFunctionInfo.cpp41 if (const auto *Sign = mdconst::extract_or_null<ConstantInt>( in GetSignReturnAddress() local
43 if (Sign->getZExtValue()) { in GetSignReturnAddress()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2428 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
2429 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2435 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2440 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
2441 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2447 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2453 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2458 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
2459 "st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth"
2598 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr,
[all …]
/llvm-project-15.0.7/clang/include/clang/Serialization/
H A DSourceLocationEncoding.h99 UIntTy Sign = (V & (1 << (UIntBits - 1))) ? UIntTy(-1) : UIntTy(0); in zigZag() local
100 return Sign ^ (V << 1); in zigZag()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1028 enum class ExtendKind { Zero, Sign, Unknown }; enumerator
1238 bool IsSigned = getExtendKind(NarrowDef) == ExtendKind::Sign; in cloneBitwiseIVUser()
1303 bool SignExtend = getExtendKind(NarrowDef) == ExtendKind::Sign; in cloneArithmeticIVUser()
1375 if (ExtKind == ExtendKind::Sign && OBO->hasNoSignedWrap()) in getExtendedOperandRecurrence()
1427 ExtKind = ExtendKind::Sign; in getWideRecurrence()
1432 } else if (getExtendKind(DU.NarrowDef) == ExtendKind::Sign) { in getWideRecurrence()
1434 ExtKind = ExtendKind::Sign; in getWideRecurrence()
1481 bool IsSigned = getExtendKind(DU.NarrowDef) == ExtendKind::Sign; in widenLoopCompare()
1579 if (ExtKind == ExtendKind::Sign && ICmpInst::isUnsigned(Pred)) in widenWithVariantUse()
1584 if (ExtKind == ExtendKind::Sign) in widenWithVariantUse()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MachineFunctionInfo.cpp46 if (const auto *Sign = mdconst::extract_or_null<ConstantInt>( in GetSignReturnAddress() local
48 if (Sign->getZExtValue()) { in GetSignReturnAddress()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp92 int Sign = 1; in inc() local
95 Sign = -1; in inc()
102 Value[Kind] += Sign; in inc()
111 Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask); in inc()
115 Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight(); in inc()
/llvm-project-15.0.7/flang/lib/Semantics/
H A Dcheck-io.cpp145 case ParseKind::Sign: in Enter()
146 specKind = IoSpecKind::Sign; in Enter()
404 case ParseKind::Sign: in Enter()
405 specKind = IoSpecKind::Sign; in Enter()
523 case ParseKind::Sign: in Enter()
524 specKind = IoSpecKind::Sign; in Enter()
761 CheckForProhibitedSpecifier(IoSpecKind::Sign); // C1212 in Leave()
798 IoSpecKind::Sign, flags_.test(Flag::FmtOrNml), "FMT or NML"); // C1227 in Leave()
869 {IoSpecKind::Sign, {"PLUS", "PROCESSOR_DEFINED", "SUPPRESS"}}, in CheckStringValue()
/llvm-project-15.0.7/flang/include/flang/Common/
H A Dformat.h45 Star, LParen, RParen, Comma, Point, Sign, in ENUM_CLASS() argument
383 token_.set_kind(TokenKind::Sign); in NextToken()
582 if (token_.kind() == TokenKind::Sign) { in Check()
686 if (token_.kind() == TokenKind::Sign) { in Check()
880 case TokenKind::Sign: // Error; main switch has a better message. in Check()
H A DFortran.h53 Pending, Pos, Position, Read, Readwrite, Rec, Recl, Round, Sequential, Sign,
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dsext_64_32.ll4 ; Sign extend from 32 to 64 was creating nonsense opcodes
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DCmpInstAnalysis.h54 Constant *getPredForICmpCode(unsigned Code, bool Sign, Type *OpTy,
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp135 int64_t Sign = 1; in isAddConstantOp() local
138 Sign = -1; in isAddConstantOp()
142 Amount = Sign * MI.getOperand(2).getImm(); in isAddConstantOp()
/llvm-project-15.0.7/polly/lib/Analysis/
H A DScopInfo.cpp1926 if (Sign == AS_ASSUMPTION) { in isEffectiveAssumption()
1943 AssumptionSign Sign, BasicBlock *BB) { in trackAssumption() argument
1944 if (PollyRemarksMinimal && !isEffectiveAssumption(Set, Sign)) in trackAssumption()
1950 if (Sign == AS_ASSUMPTION) in trackAssumption()
1953 bool IsTrivial = (Sign == AS_RESTRICTION && Set.is_empty()) || in trackAssumption()
1954 (Sign == AS_ASSUMPTION && Univ.is_equal(Set)); in trackAssumption()
2006 AssumptionSign Sign, BasicBlock *BB, in addAssumption() argument
2010 intersectDefinedBehavior(Set, Sign); in addAssumption()
2015 if (!trackAssumption(Kind, Set, Loc, Sign, BB)) in addAssumption()
2018 if (Sign == AS_ASSUMPTION) in addAssumption()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-ret.ll5 ; Sign-extend of i1 currently not supported by fast-isel
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DSpecifiers.h101 /*DeclSpec::TSS*/ unsigned Sign : 2; member

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