Searched refs:ShiftedVal (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 185 int64_t ShiftedVal = Val >> TrailingZeros; in generateInstSeq() local
187 generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq); in generateInstSeq()
205 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros; in generateInstSeq() local
209 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros); in generateInstSeq()
212 generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq); in generateInstSeq()
224 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros); in generateInstSeq()
226 generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq); in generateInstSeq()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 215 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
217 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
218 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4121 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
4125 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4126 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4129 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
4132 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
4133 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
4134 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
4138 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4145 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
4146 if (!CanShrinkImmediate(ShiftedVal)) in tryShrinkShlLogicImm()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 933 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
934 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
946 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
947 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1691 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1692 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1693 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1706 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1707 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1708 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14351 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine() local
14354 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0; in performMulCombine()
14355 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal; in performMulCombine()
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