Searched refs:ShiftRightOp (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 294 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts() local
308 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in lowerShiftRightParts()
309 SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusGRLen); in lowerShiftRightParts()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3316 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in LowerShiftRightParts() local
3332 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in LowerShiftRightParts()
3334 DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize); in LowerShiftRightParts()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4102 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts() local
4116 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in lowerShiftRightParts()
4117 SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen); in lowerShiftRightParts()
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